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| author | pekon gupta <pekon@ti.com> | 2014-07-22 16:03:23 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-08-25 10:48:12 -0400 |
| commit | 54a97d2849979acd84a0475486edf0d0c18e47c7 (patch) | |
| tree | 32b50e60590a8dab8d7f44d9c471f0a6ad830cc6 /board | |
| parent | e53ad4b445464327aebd1c5ea6260b7bb9b80ae7 (diff) | |
| download | u-boot-imx-54a97d2849979acd84a0475486edf0d0c18e47c7.zip u-boot-imx-54a97d2849979acd84a0475486edf0d0c18e47c7.tar.gz u-boot-imx-54a97d2849979acd84a0475486edf0d0c18e47c7.tar.bz2 | |
board/ti/dra7xx: add support for parallel NAND
This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
chip-select[0] on DRA7xx EVM.
As GPMC pins are shared by multiple devices, so in addition to this patch
following board settings are required for NAND device detection [1]:
SW5.9 (GPMC_WPN) = OFF (logic-1)
SW5.1 (NAND_BOOTn) = ON (logic-0) /* Active-low */
SW5.2 (NOR_BOOTn) = OFF (logic-1)
SW5.3 (eMMC_BOOTn) = OFF (logic-1)
SW5.4 (QSPI_BOOTn) = OFF (logic-1)
And also set appropriate SYSBOOT configurations
SW2.1 (SYSBOOT[0]) = ON (logic-1) /* selects NAND Boot */
SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */
SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */
SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */
SW2.5 (SYSBOOT[4]) = ON (logic-1) /* selects NAND Boot */
SW2.6 (SYSBOOT[5]) = ON (logic-1) /* selects NAND Boot */
SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */
SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */
SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */
SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */
SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */
SW3.5 (SYSBOOT[12])= ON (logic-1) /* device type: Addr/Data Muxed */
SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */
SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */
Following changes are required in board.cfg to enable NAND on J6-EVM:
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/dra7xx/mux_data.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 7db7032..1ea236b 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -68,6 +68,33 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {VIN2A_D21, (IEN | M3)}, {VIN2A_D22, (IEN | M3)}, {VIN2A_D23, (IEN | M3)}, +#ifdef CONFIG_NAND + /* NAND / NOR pin-mux */ + {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ + {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */ + {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */ + {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */ + {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */ + {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */ + {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */ + {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */ + {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */ + {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */ + {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */ + {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */ + {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */ + {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */ + {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */ + {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */ + {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */ + {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */ + {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */ + {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */ + {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */ + {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */ + /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */ +#else + /* QSPI pin-mux */ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ @@ -78,6 +105,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ +#endif /* CONFIG_NAND */ {USB2_DRVVBUS, (M0 | IEN | FSC) }, }; #endif /* _MUX_DATA_DRA7XX_H_ */ |