Merge git://git.denx.de/u-boot

author: Stefano Babic <sbabic@denx.de> 2012-11-10 08:05:54 +0100
committer: Stefano Babic <sbabic@denx.de> 2012-11-10 08:05:54 +0100
commit: 3e4d27b06d7484040355e22eec2cbce7335d6dab (patch)
tree: 9672a2bb2e4ce0edc0ab776ddf0e2ca8e39a5f62 /board
parent: bad05afe083eec0467220de21683443292c5012e (diff)
parent: 59852d03867108217fe88e3bfc3e1e9cedfe63c5 (diff)
download: u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.zip
u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.gz
u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.bz2
267 files changed, 5860 insertions, 13351 deletions
diff --git a/board/lantec/Makefile b/board/8dtech/eco5pk/Makefile
index 12e4aa6..befe60a 100644
--- a/board/lantec/Makefile
+++ b/board/8dtech/eco5pk/Makefile
@@ -1,7 +1,9 @@
 #
-# (C) Copyright 2001-2006
+# (C) Copyright 2000, 2001, 2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# Adapted from ti/evm/Makefile
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -25,11 +27,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	= $(BOARD).o flash.o
+COBJS	:= eco5pk.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
@@ -40,5 +41,3 @@ $(LIB):	$(obj).depend $(OBJS)
 include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/8dtech/eco5pk/eco5pk.c b/board/8dtech/eco5pk/eco5pk.c
new file mode 100644
index 0000000..cdb5b6f
--- /dev/null
+++ b/board/8dtech/eco5pk/eco5pk.c
@@ -0,0 +1,61 @@
+/*
+ * eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board
+ *
+ * Based on am3517evm.c
+ *
+ * Copyright (C) 2011-2012 8D Technologies inc.
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <crc.h>
+#include <asm/mach-types.h>
+#include "eco5pk.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	gpio_request(30, "RESOUT");
+	gpio_direction_output(30, 1);
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_ECO5_PK();
+}
diff --git a/board/8dtech/eco5pk/eco5pk.h b/board/8dtech/eco5pk/eco5pk.h
new file mode 100644
index 0000000..d289e2b
--- /dev/null
+++ b/board/8dtech/eco5pk/eco5pk.h
@@ -0,0 +1,404 @@
+/*
+ * eco5.h - Header file for the 8D Technologies ECO5 board.
+ *
+ * Based on  am3517evm.h
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2011 8D Technologies inc.
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _ECO5PK_H__
+#define _ECO5PK_H__
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"ECO5 Board",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_ECO5_PK() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS  | PTU | DIS | M3)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | DIS  | M4)) \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) \
+							 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) \
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(DSS_DATA1),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(DSS_DATA2),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(DSS_DATA3),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(DSS_DATA4),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(DSS_DATA5),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(DSS_DATA6),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(DSS_DATA7),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) \
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /* LED ACT */ \
+	\
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
+							/* LCD_EN_BACKLIGHT */\
+	MUX_VAL(CP(MCSPI2_CS1),		(IDIS | PTD | EN  | M4)) \
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
+							/* SYS_nRESWARM */\
+	MUX_VAL(CP(SYS_NRESWARM),	(IDIS | PTU | DIS | M4)) \
+							/* - GPIO30 */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /* GPIO_2 */\
+							 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /* GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /* GPIO_4 */\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /* GPIO_5 */\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /* GPIO_6 */\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /* GPIO_7 */\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /* GPIO_8 */\
+							 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0))
+
+#endif
diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds
index 4ba1964..0c92d31 100644
--- a/board/BuS/eb_cpu5282/u-boot.lds
+++ b/board/BuS/eb_cpu5282/u-boot.lds
@@ -65,9 +65,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds
index 5aaf6b3..2bb876d 100644
--- a/board/LEOX/elpt860/u-boot.lds
+++ b/board/LEOX/elpt860/u-boot.lds
@@ -86,9 +86,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
index 1327c62..4a780c3 100644
--- a/board/Marvell/common/serial.c
+++ b/board/Marvell/common/serial.c
@@ -139,20 +139,13 @@ static void marvell_serial_setbrg(void)
 
 #endif /* CONFIG_MPSC */
 
-static void marvell_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
 static struct serial_device marvell_serial_drv = {
 	.name	= "marvell_serial",
 	.start	= marvell_serial_init,
 	.stop	= NULL,
 	.setbrg	= marvell_serial_setbrg,
 	.putc	= marvell_serial_putc,
-	.puts	= marvell_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= marvell_serial_getc,
 	.tstc	= marvell_serial_tstc,
 };
diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/RPXClassic/u-boot.lds
+++ b/board/RPXClassic/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug
index 99c48f2..dc8c4e9 100644
--- a/board/RPXClassic/u-boot.lds.debug
+++ b/board/RPXClassic/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/RPXlite/u-boot.lds
+++ b/board/RPXlite/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug
index 99c48f2..dc8c4e9 100644
--- a/board/RPXlite/u-boot.lds.debug
+++ b/board/RPXlite/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/RPXlite_dw/u-boot.lds
+++ b/board/RPXlite_dw/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug
index 4491edd..b43a1e4 100644
--- a/board/RPXlite_dw/u-boot.lds.debug
+++ b/board/RPXlite_dw/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds
index 8385373..748e511 100644
--- a/board/RRvision/u-boot.lds
+++ b/board/RRvision/u-boot.lds
@@ -71,9 +71,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index 9dbaa6f..c41eed0 100644
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
 		net/libnet.o(.text*)
 		board/actux1/libactux1.o(.text*)
 		arch/arm/cpu/ixp/libixp.o(.text*)
-		drivers/serial/libserial.o(.text*)
+		drivers/input/libinput.o(.text*)
 
 		. = env_offset;
 		common/env_embedded.o(.ppcenv)
@@ -54,11 +54,11 @@ SECTIONS
 		*(.got)
 	}
 	. =.;
-	__u_boot_cmd_start =.;
-	.u_boot_cmd : {
-		*(.u_boot_cmd)
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
 	}
-	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
 	.rel.dyn : {
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index 3575ed9..8409984 100644
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
 		net/libnet.o(.text*)
 		board/actux2/libactux2.o(.text*)
 		arch/arm/cpu/ixp/libixp.o(.text*)
-		drivers/serial/libserial.o(.text*)
+		drivers/input/libinput.o(.text*)
 
 		. = env_offset;
 		common/env_embedded.o(.ppcenv)
@@ -54,11 +54,11 @@ SECTIONS
 		*(.got)
 	}
 	. =.;
-	__u_boot_cmd_start =.;
-	.u_boot_cmd : {
-		*(.u_boot_cmd)
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
 	}
-	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
 	.rel.dyn : {
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 35aab29..a3bd02b 100644
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
 		net/libnet.o(.text*)
 		board/actux3/libactux3.o(.text*)
 		arch/arm/cpu/ixp/libixp.o(.text*)
-		drivers/serial/libserial.o(.text*)
+		drivers/input/libinput.o(.text*)
 
 		. = env_offset;
 		common/env_embedded.o(.ppcenv)
@@ -54,11 +54,11 @@ SECTIONS
 		*(.got)
 	}
 	. =.;
-	__u_boot_cmd_start =.;
-	.u_boot_cmd : {
-		*(.u_boot_cmd)
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
 	}
-	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
 	.rel.dyn : {
diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds
index a762769..73e2f3f 100644
--- a/board/adder/u-boot.lds
+++ b/board/adder/u-boot.lds
@@ -62,9 +62,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
index 52c986e..656b2fb 100644
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -48,6 +48,10 @@ SECTIONS
 	. = ALIGN(4);
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 	. = ALIGN(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
+	} >.sram
+	. = ALIGN(4);
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
index 88ced62..289386b 100644
--- a/board/altera/nios2-generic/u-boot.lds
+++ b/board/altera/nios2-generic/u-boot.lds
@@ -46,13 +46,11 @@ SECTIONS
 	 * the initialization code relocates the command table as
 	 * well -- admittedly, this is just pure laziness ;-)
 	 */
-	__u_boot_cmd_start = .;
-	.u_boot_cmd :
-	{
-	  *(.u_boot_cmd)
-	}
+
 	. = ALIGN(4);
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	/* INIT DATA sections - "Small" data (see the gcc -G option)
 	 * is always gp-relative. Here we make all init data sections
diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds
index ab67de2..beba978 100644
--- a/board/amcc/acadia/u-boot-nand.lds
+++ b/board/amcc/acadia/u-boot-nand.lds
@@ -72,10 +72,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds
index 3ad8709..2dd00d7 100644
--- a/board/amcc/bamboo/u-boot-nand.lds
+++ b/board/amcc/bamboo/u-boot-nand.lds
@@ -73,10 +73,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds
index 76f89f1..8ac5116 100644
--- a/board/amcc/canyonlands/u-boot-nand.lds
+++ b/board/amcc/canyonlands/u-boot-nand.lds
@@ -73,10 +73,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds
index ab67de2..beba978 100644
--- a/board/amcc/kilauea/u-boot-nand.lds
+++ b/board/amcc/kilauea/u-boot-nand.lds
@@ -72,10 +72,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds
index 07ae8b1..18266ef 100644
--- a/board/amcc/sequoia/u-boot-nand.lds
+++ b/board/amcc/sequoia/u-boot-nand.lds
@@ -73,10 +73,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds
index 423400a..6b02784 100644
--- a/board/amcc/sequoia/u-boot-ram.lds
+++ b/board/amcc/sequoia/u-boot-ram.lds
@@ -64,10 +64,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds
index a1d8e0f..bc40fd6 100644
--- a/board/astro/mcf5373l/u-boot.lds
+++ b/board/astro/mcf5373l/u-boot.lds
@@ -22,51 +22,18 @@
  */
 
 OUTPUT_ARCH(m68k)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
+
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
   .text      :
   {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/m68k/cpu/mcf532x/start.o		(.text)
-    arch/m68k/lib/traps.o		(.text)
-    arch/m68k/lib/interrupts.o	(.text)
-    common/dlmalloc.o		(.text)
-    lib/zlib.o		(.text)
+    arch/m68k/cpu/mcf532x/start.o		(.text*)
 
     . = DEFINED(env_offset) ? env_offset : .;
-    common/env_embedded.o	(.text)
+    common/env_embedded.o	(.text*)
 
-    *(.text)
-/*    *(.fixup)*/
-    *(.got1)
+    *(.text*)
   }
   _etext = .;
   PROVIDE (etext = .);
@@ -74,9 +41,6 @@ SECTIONS
   {
     *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
   }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
 
   /* Read-write section, merged into data segment: */
   . = (. + 0x00FF) & 0xFFFFFF00;
@@ -86,33 +50,30 @@ SECTIONS
   .reloc   :
   {
     __got_start = .;
-    *(.got)
+    KEEP(*(.got))
     __got_end = .;
     _GOT2_TABLE_ = .;
-    *(.got2)
+    KEEP(*(.got2))
     _FIXUP_TABLE_ = .;
-    *(.fixup)
+    KEEP(*(.fixup))
   }
   __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
   __fixup_entries = (. - _FIXUP_TABLE_)>>2;
 
   .data    :
   {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
+    *(.data*)
+    *(.sdata*)
   }
   _edata  =  .;
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
@@ -130,9 +91,8 @@ SECTIONS
   .bss       :
   {
    _sbss = .;
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
+   *(.sbss*)
+   *(.bss*)
    *(COMMON)
    . = ALIGN(4);
    _ebss = .;
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 06028aa..edb0886 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -31,6 +31,7 @@
 #include <asm/arch/clk.h>
 #include <lcd.h>
 #include <atmel_hlcdc.h>
+#include <atmel_mci.h>
 #ifdef CONFIG_MACB
 #include <net.h>
 #endif
@@ -258,6 +259,15 @@ void spi_cs_deactivate(struct spi_slave *slave)
 }
 #endif /* CONFIG_ATMEL_SPI */
 
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	at91_seriald_hw_init();
diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile
index 864bc0e..e8c1e8b 100644
--- a/board/avionic-design/medcom-wide/Makefile
+++ b/board/avionic-design/medcom-wide/Makefile
@@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= ../../nvidia/common/board.o
-COBJS	+= ../common/tamonten.o
+COBJS-y	:= ../common/tamonten.o
 
+include ../../nvidia/common/common.mk
+
+COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile
index 864bc0e..e8c1e8b 100644
--- a/board/avionic-design/plutux/Makefile
+++ b/board/avionic-design/plutux/Makefile
@@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= ../../nvidia/common/board.o
-COBJS	+= ../common/tamonten.o
+COBJS-y	:= ../common/tamonten.o
 
+include ../../nvidia/common/common.mk
+
+COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile
index 864bc0e..e8c1e8b 100644
--- a/board/avionic-design/tec/Makefile
+++ b/board/avionic-design/tec/Makefile
@@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= ../../nvidia/common/board.o
-COBJS	+= ../common/tamonten.o
+COBJS-y	:= ../common/tamonten.o
 
+include ../../nvidia/common/common.mk
+
+COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/board/bmw/Makefile b/board/bmw/Makefile
deleted file mode 100644
index 4f88efa..0000000
--- a/board/bmw/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ns16550.o serial.o m48t59y.o
-
-SOBJS	= early_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/bmw/README b/board/bmw/README
deleted file mode 100644
index 1fbef79..0000000
--- a/board/bmw/README
+++ /dev/null
@@ -1,331 +0,0 @@
-Broadcom 95xx BMW CPCI Platform
-
-Overview
-=========
-BMW is an MPC8245 system controller featuring:
-* 3U CPCI Form Factor
-* BCM5703 Gigabit Ethernet
-* M48T59Y NVRAM
-* 16MB DOC
-* DIP Socket for Socketed DOC up to 1GB
-* 64MB SDRAM
-* LCD Display
-* Configurable Jumper options for 66,85, and 100Mhz memory bus
-
-
-BMW System Address Map
-======================
-BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual
-(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found
-onboard the processor module are listed briefly below:
-
-0x00000000 - 0x40000000 - 64MB SDRAM SIMM
-			  (Unregistered PC-100 SDRAM DIMM Module)
-
-0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000
-			  TSOP 16MB (MD2211-D16-V3)
-
-0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000
-			  DIP32 (Socketed 16MB - 1GB ) *
-			  NOTE: this is not populated on all systems.
-
-0x7c000000 - 0x7c000000 - Reset Register
-			  (Write 0 to reset)
-
-0x7c000001 - 0x7c000001 - System LED
-			  (Clear Bit 7 to turn on, set to shut off)
-
-0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3
-			  (Clear bit 7 to reset, set to assert IRQ3)
-
-0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register
-			  (Clear bit 7 to make R/W, set to make R/O)
-
-0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character
-			  5x7 Dot Matrix Alphanumeric Display
-			  (Each byte sets the appropriate character)
-
-0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC
-			  NVRAM Memory Region
-
-0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC
-			  Realtime Clock Registers
-
-0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom
-			  (AMD AM29F040, ST 29W040B)
-
-0xFFF00100 -              System Reset Vector
-
-
-IO/MMU (BAT) Configuration
-======================
-The following Block-Address-Translation (BAT) configuration
-is recommended to access all I/O devices.
-
-#define CONFIG_SYS_IBAT0L  (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U  (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
-
-
-Interrupt Mappings
-======================
-BMW uses MPC8245 discrete mode interrupts. With the following
-hardwired mappings:
-
-BCM5701 10/100/1000 Ethernet		IRQ1
-CompactPCI Interrupt A			IRQ2
-RTC/Watchdog Interrupt			IRQ3
-Internal NS16552 UART			IRQ4
-
-
-Jumper Settings
-======================
-
-BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus.
-A jumper (X) is a 0 bit.
-
-Hence 66= 10110
-      85= 11000
-     100= 10000
-
-Jumper Settings for various Speeds
-=======================
-J1 J2 J3 J4 J5
-    X        X    66Mhz
-=======================
-J1 J2 J3 J4 J5
-       X  X  X    85Mhz
-=======================
-J1 J2 J3 J4 J5
-    X  X  X  X   100Mhz
-=======================
-
-Obviously, 100Mhz memory bus is recommended for optimum performance.
-
-
-U-Boot
-===============
-Broadcom BMW board is supported under config_BWM option.
-Supported features:
-
-- NVRAM setenv/getenv (used by Linux Kernel for configuration variables)
-- BCM570x TFTP file transfer support
-- LCD Display Support
-- DOC Support - (underway)
-
-
-U-Boot 1.2.0 (Aug  6 2002 - 17:44:48)
-
-CPU:   MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
-Built: Aug  6 2002 at 17:44:37
-Local Bus at 66 MHz
-DRAM:  64 MB
-FLASH: 4095 MB
-In:    serial
-Out:   serial
-Err:   serial
-DOC:   No DiskOnChip found
-Hit any key to stop autoboot:  0
-=>printenv
-bootdelay=5
-baudrate=9600
-clocks_in_mhz=1
-hostname=switch-2
-bootcmd=tftp 100000 vmlinux.img;bootm
-gateway=10.16.64.1
-ethaddr=00:00:10:18:10:10
-nfsroot=172.16.40.111:/boot/root-fs
-filesize=5ec8c
-netmask=255.255.240.0
-ipaddr=172.16.40.114
-serverip=172.16.40.111
-root=/dev/nfs
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 315/8172 bytes
-=>boot
-
-
-DevTools
-========
-ELDK
-	DENX Embedded Linux Development Kit
-
-ROM Emulator
-	Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time)
-	Grammar Engine PL32E 32Pin PLCC Emulation cables
-	Grammar Engine 3VA8CON (3Volt adapter with Short cables)
-	Grammar Engine FPNET PromICE Ethernet Adapters
-
-ICE
-	WRS/EST VisionICE-II (PPC8240)
-
-
-=>reset
-
-
-U-Boot 1.2.0 (Aug  6 2002 - 17:44:48)
-
-CPU:   MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
-Built: Aug  6 2002 at 17:44:37
-Local Bus at 66 MHz
-DRAM:  64 MB
-FLASH: 4095 MB
-In:    serial
-Out:   serial
-Err:   serial
-DOC:   No DiskOnChip found
-Hit any key to stop autoboot:  0
-
-Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000
-BCM570x PCI Memory base address @0x80100000
-eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF
-eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010
-eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found
-eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON
-ARP broadcast 1
-TFTP from server 172.16.40.111; our IP address is 172.16.40.114
-Filename 'vmlinux.img'.
-Load address: 0x100000
-Loading: #################################################################
-	 ####################################T #############################
-	 ######################
-done
-Bytes transferred = 777199 (bdbef hex)
-
-eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline.
-## Booting image at 00100000 ...
-   Image Name:   vmlinux.bin.gz
-   Created:      2002-08-06   6:30:13 UTC
-   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
-   Data Size:    777135 Bytes = 758 kB = 0 MB
-   Load Address: 00000000
-   Entry Point:  00000000
-   Verifying Checksum ... OK
-   Uncompressing Kernel Image ... OK
-Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb
-Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002
-CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000
-U-Boot Environment: 0xc01b08f0
-IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10>
-cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e
-NOTICE: mounting root file system via NFS
-IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111
-On node 0 totalpages: 16384
-zone(0): 16384 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111
-root_dev_setup:/dev/nfs or 00:ff
-time_init: decrementer frequency = 16.501145 MHz
-Calibrating delay loop... 175.71 BogoMIPS
-Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem)
-Dentry cache hash table entries: 8192 (order: 4, 65536 bytes)
-Inode cache hash table entries: 4096 (order: 3, 32768 bytes)
-Mount-cache hash table entries: 1024 (order: 1, 8192 bytes)
-Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
-Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
-POSIX conformance testing by UNIFIX
-PCI: Probing PCI hardware
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Initializing RT netlink socket
-Starting kswapd
-devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au)
-devfs: devfs_debug: 0x0
-devfs: boot_options: 0x1
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
-pty: 256 Unix98 ptys configured
-Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
-Testing ttyS0 (0xf7f51500, 0xf7f51500)...
-Testing ttyS1 (0xfc004600, 0xfc004600)...
-ttyS00 at 0xf7f51500 (irq = 24) is a ST16650
-ttyS01 at 0xfc004600 (irq = 25) is a 16550A
-Real Time Clock Driver v1.10e
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-loop: loaded (max 8 devices)
-TFFS 5.1.1 Flash disk driver for DiskOnChip
-Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd.
-DOC device(s) found: 1
-fl_init: registered device at major: 100
-fl_geninit: registered device at major: 100
-Partition check:
- fla: p1
-partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB
-partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB
-partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
-partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
-Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02)
-eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010
-eth0: Broadcom BCM5701 Integrated Copper transceiver found
-eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON
-bond0 registered without MII link monitoring, in bonding mode.
-rtc: unable to get misc minor
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP, IGMP
-IP: routing cache hash table of 512 buckets, 4Kbytes
-TCP: Hash tables configured (established 4096 bind 4096)
-bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex
-IP-Config: Gateway not on directly connected network.
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-802.1Q VLAN Support v1.7 Ben Greear <greearb@candelatech.com>
-All bugs added by David S. Miller <davem@redhat.com>
-Looking up port of RPC 100003/2 on 172.16.40.111
-Looking up port of RPC 100005/1 on 172.16.40.111
-VFS: Mounted root (nfs filesystem).
-Mounted devfs on /dev
-Freeing unused kernel memory: 100k init
-INIT: version 2.78 booting
-Mounting local filesystems...
-not mounted anything
-Setting up symlinks in /dev...done.
-Setting up extra devices in /dev...done.
-Starting devfsd...Started device management daemon for /dev
-INIT: Entering runlevel: 2
-Starting internet superserver: inetd.
-
-
-Welcome to Linux/PPC
-MPC8245/BMW
-
-
-switch-2 login: root
-Password:
-PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0)
-Last login: Thu Nov 25 11:51:14 1920 on console
-
-
-Welcome to Linux/PPC
-MPC8245/BMW
-
-
-login[49]: ROOT LOGIN on `console'
-
-root@switch-2:~# cat /proc/cpuinfo
-cpu             : 82xx
-revision        : 16.20 (pvr 8081 1014)
-bogomips        : 175.71
-vendor          : Broadcom
-machine         : BMW/MPC8245
-root@switch-2:~#
diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c
deleted file mode 100644
index 5ba6c09..0000000
--- a/board/bmw/bmw.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2002
- * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <net.h>
-#include <timestamp.h>
-#include <dtt.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <linux/mtd/doc2000.h>
-
-#include "bmw.h"
-#include "m48t59y.h"
-#include <pci.h>
-
-
-int checkboard(void)
-{
-    ulong busfreq  = get_bus_freq(0);
-    char  buf[32];
-
-    puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
-    printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
-    /* printf("MPLD:  Revision %d\n", SYS_REVID_GET()); */
-    printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
-    return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-    return 64*1024*1024;
-}
-
-
-void
-get_tod(void)
-{
-    int year, month, day, hour, minute, second;
-
-    m48_tod_get(&year,
-		&month,
-		&day,
-		&hour,
-		&minute,
-		&second);
-
-    printf("  Current date/time: %d/%d/%d %d:%d:%d \n",
-	   month, day, year, hour, minute, second);
-
-}
-
-/*
- * EPIC, PCI, and I/O devices.
- * Initialize Mousse Platform, probe for PCI devices,
- * Query configuration parameters if not set.
- */
-int misc_init_f (void)
-{
-#if 0
-    m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */
-    printf("RTC:   M48T589 TOD/NVRAM (%d) bytes\n",
-	   TOD_NVRAM_SIZE);
-    get_tod();
-#endif
-
-    sys_led_msg("BOOT");
-    return 0;
-}
-
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-struct pci_controller hose;
-
-void pci_init_board (void)
-{
-    pci_mpc824x_init(&hose);
-    /* pci_dev_init(0); */
-}
-
-/*
- * Write characters to LCD display.
- * Note that the bytes for the first character is the last address.
- */
-void
-sys_led_msg(char* msg)
-{
-    LED_REG(0) = msg[3];
-    LED_REG(1) = msg[2];
-    LED_REG(2) = msg[1];
-    LED_REG(3) = msg[0];
-}
-
-#ifdef CONFIG_CMD_DOC
-/*
- * Map onboard TSOP-16MB DOC FLASH chip.
- */
-void doc_init (void)
-{
-    doc_probe(DOC_BASE_ADDR);
-}
-#endif
-
-#define NV_ADDR	((volatile unsigned char *) CONFIG_ENV_ADDR)
-
-/* Read from NVRAM */
-void*
-nvram_read(void *dest, const long src, size_t count)
-{
-    int i;
-    volatile unsigned char* d = (unsigned char*)dest;
-    volatile unsigned char* s = (unsigned char*)src;
-
-    for( i = 0; i < count;i++)
-	d[i] = s[i];
-
-    return dest;
-}
-
-/* Write to NVRAM */
-void
-nvram_write(long dest, const void *src, size_t count)
-{
-    int i;
-    volatile unsigned char* d = (unsigned char*)dest;
-    volatile unsigned char* s = (unsigned char*)src;
-
-    SYS_TOD_UNPROTECT();
-
-    for( i = 0; i < count;i++)
-	d[i] = s[i];
-
-    SYS_TOD_PROTECT();
-}
diff --git a/board/bmw/bmw.h b/board/bmw/bmw.h
deleted file mode 100644
index dd97569..0000000
--- a/board/bmw/bmw.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * BMW/MPC8245 Board definitions.
- * For more info, see http://www.vooha.com/
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * James Dougherty (jfd@broadcom.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __BMW_H
-#define __BMW_H
-
-/* System addresses */
-
-#define PCI_SPECIAL_BASE	0xfe000000
-#define PCI_SPECIAL_SIZE	0x01000000
-
-#define EUMBBAR_VAL		0x80500000	/* Location of EUMB region */
-#define EUMBSIZE		0x00100000	/* Size of EUMB region */
-
-/* Extended ROM space devices */
-#define DOC_BASE_ADDR           0xff000000      /* Onboard DOC TSOP 16MB */
-#define DOC2_BASE_ADDR          0x70000000      /* DIP32 socket -> 1GB */
-#define XROM_BASE_ADDR          0x7c000000      /* RCS2 (PAL / Satellite IO) */
-#define PLD_REG_BASE		XROM_BASE_ADDR
-#define LED_REG_BASE		(XROM_BASE_ADDR | 0x2000)
-#define TOD_BASE		(XROM_BASE_ADDR | 0x4000)
-#define LED_REG(x)              (*(volatile unsigned char *) \
-				  (LED_REG_BASE + (x)))
-#define XROM_DEV_SIZE		0x00006000
-
-#define ENET_DEV_BASE		0x80000000
-
-#define PLD_REG(off)		(*(volatile unsigned char *)\
-				  (PLD_REG_BASE + (off)))
-
-#define PLD_REVID_B1		0x7f	/* Fix me */
-#define PLD_REVID_B2		0x01	/* Fix me */
-
-#define SYS_HARD_RESET()	{ for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
-#define SYS_REVID_GET()		((int) PLD_REG(0) & 0x7f)
-#define SYS_LED_OFF()		(PLD_REG(1) |= 0x80)
-#define SYS_LED_ON()		(PLD_REG(1) &= ~0x80)
-#define SYS_WATCHDOG_IRQ3()	(PLD_REG(2) |= 0x80)
-#define SYS_WATCHDOG_RESET()	(PLD_REG(2) &= ~0x80)
-#define SYS_TOD_PROTECT()	(PLD_REG(3) |= 0x80)
-#define SYS_TOD_UNPROTECT()	(PLD_REG(3) &= ~0x80)
-
-#define	TOD_REG_BASE		(TOD_BASE | 0x1ff0)
-#define	TOD_NVRAM_BASE		TOD_BASE
-#define	TOD_NVRAM_SIZE		0x1ff0
-#define	TOD_NVRAM_LIMIT		(TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
-#define RTC(r)		        (TOD_BASE + r)
-
-/* Onboard BCM570x device */
-#define	PCI_ENET_IOADDR		0x80000000
-#define	PCI_ENET_MEMADDR	0x80000000
-
-
-#ifndef __ASSEMBLY__
-/* C Function prototypes */
-void sys_led_msg(char* msg);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __BMW_H */
diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S
deleted file mode 100644
index 63c29d5..0000000
--- a/board/bmw/early_init.S
+++ /dev/null
@@ -1,1170 +0,0 @@
-#include <ppc_asm.tmpl>
-#include <mpc824x.h>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */
-
-
-/*
- * Initialize the MMU using BAT entries and hardwired TLB
- * This obviates the need for any code in cpu_init_f which
- * configures the BAT registers.
-*/
-#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */
-	.global	iommu_setup
-	/* Initialize IO/MMU mappings via BAT method Ch. 7,
-	 * PPC Programming Reference
-	 */
-iommu_setup:
-
-/* initialize the BAT registers (SPRs 528 - 543 */
-#define	mtibat0u(x)	mtspr	528,(x)			/* SPR 528 (IBAT0U) */
-#define mtibat0l(x)	mtspr	529,(x)			/* SPR 529 (IBAT0L) */
-#define mtibat1u(x)	mtspr	530,(x)			/* SPR 530 (IBAT1U) */
-#define mtibat1l(x)	mtspr	531,(x)			/* SPR 531 (IBAT1L) */
-#define mtibat2u(x)	mtspr	532,(x)			/* SPR 532 (IBAT2U) */
-#define mtibat2l(x)	mtspr	533,(x)			/* SPR 533 (IBAT2L) */
-#define mtibat3u(x)	mtspr	534,(x)			/* SPR 534 (IBAT3U) */
-#define mtibat3l(x)	mtspr	535,(x)			/* SPR 535 (IBAT3L) */
-#define mtdbat0u(x)	mtspr	536,(x)			/* SPR 536 (DBAT0U) */
-#define mtdbat0l(x)	mtspr	537,(x)			/* SPR 537 (DBAT0L) */
-#define mtdbat1u(x)	mtspr	538,(x)			/* SPR 538 (DBAT1U) */
-#define mtdbat1l(x)	mtspr	539,(x)			/* SPR 539 (DBAT1L) */
-#define mtdbat2u(x)	mtspr	540,(x)			/* SPR 540 (DBAT2U) */
-#define mtdbat2l(x)	mtspr	541,(x)			/* SPR 541 (DBAT2L) */
-#define mtdbat3u(x)	mtspr	542,(x)			/* SPR 542 (DBAT3U) */
-#define mtdbat3l(x)	mtspr	543,(x)			/* SPR 543 (DBAT3L) */
-
-
-/* PowerPC processors do not necessarily initialize the BAT
-   registers on power-up or reset.  So they are in an unknown
-   state.  Before programming the BATs for the first time, all
-   BAT registers MUST have their Vs and Vp bits cleared in the
-   upper BAT half in order to avoid possibly having 2 BATs
-   valid and mapping the same memory region.
-
-   The reason for this is that, even with address translation
-   disabled, multiple BAT hits for an address are treated as
-   programming errors and can cause unpredictable results.
-
-   It is up to the software to make sure it never has 2 IBAT
-   mappings or 2 DBAT mappings that are valid for the same
-   addresses.  It is not necessary to perform this code
-   sequence every time the BATs are programmed, only when
-   there is a possibility that there may be overlapping BAT
-   entries.
-
-   When programming the BATs in non-reset scenarios, even if
-   you are sure that your new mapping will not temporarily
-   create overlapping regions, it is still a wise idea to
-   invalidate a BAT entry by setting its upper BAT register to
-   all 0's before programming it.  This will avoid having a
-   BAT marked valid that is in an unknown or transient state
-*/
-
-	addis   r5,0,0x0000
-	mtibat0u(r5)
-	mtibat0l(r5)
-	mtibat1u(r5)
-	mtibat1l(r5)
-	mtibat2u(r5)
-	mtibat2l(r5)
-	mtibat3u(r5)
-	mtibat3l(r5)
-	mtdbat0u(r5)
-	mtdbat0l(r5)
-	mtdbat1u(r5)
-	mtdbat1l(r5)
-	mtdbat2u(r5)
-	mtdbat2l(r5)
-	mtdbat3u(r5)
-	mtdbat3l(r5)
-	isync
-
-/*
- *  Set up I/D BAT0
- */
-	lis     r4, CONFIG_SYS_DBAT0L@h
-	ori     r4, r4, CONFIG_SYS_DBAT0L@l
-	lis     r3, CONFIG_SYS_DBAT0U@h
-	ori     r3, r3, CONFIG_SYS_DBAT0U@l
-
-	mtdbat0l(r4)
-	isync
-	mtdbat0u(r3)
-	isync
-	sync
-
-	lis     r4, CONFIG_SYS_IBAT0L@h
-	ori     r4, r4, CONFIG_SYS_IBAT0L@l
-	lis     r3, CONFIG_SYS_IBAT0U@h
-	ori     r3, r3, CONFIG_SYS_IBAT0U@l
-
-	isync
-	mtibat0l(r4)
-	isync
-	mtibat0u(r3)
-	isync
-
-/*
- *  Set up I/D BAT1
- */
-	lis     r4, CONFIG_SYS_IBAT1L@h
-	ori     r4, r4, CONFIG_SYS_IBAT1L@l
-	lis     r3, CONFIG_SYS_IBAT1U@h
-	ori     r3, r3, CONFIG_SYS_IBAT1U@l
-
-	isync
-	mtibat1l(r4)
-	isync
-	mtibat1u(r3)
-	isync
-	mtdbat1l(r4)
-	isync
-	mtdbat1u(r3)
-	isync
-	sync
-
-/*
- *  Set up I/D BAT2
- */
-	lis     r4, CONFIG_SYS_IBAT2L@h
-	ori     r4, r4, CONFIG_SYS_IBAT2L@l
-	lis     r3, CONFIG_SYS_IBAT2U@h
-	ori     r3, r3, CONFIG_SYS_IBAT2U@l
-
-	isync
-	mtibat2l(r4)
-	isync
-	mtibat2u(r3)
-	isync
-	mtdbat2l(r4)
-	isync
-	mtdbat2u(r3)
-	isync
-	sync
-
-/*
- *  Setup I/D BAT3
- */
-	lis     r4, CONFIG_SYS_IBAT3L@h
-	ori     r4, r4, CONFIG_SYS_IBAT3L@l
-	lis     r3, CONFIG_SYS_IBAT3U@h
-	ori     r3, r3, CONFIG_SYS_IBAT3U@l
-
-	isync
-	mtibat3l(r4)
-	isync
-	mtibat3u(r3)
-	isync
-	mtdbat3l(r4)
-	isync
-	mtdbat3u(r3)
-	isync
-	sync
-
-
-/*
- *  Invalidate all 64 TLB's
- */
-	lis     r3, 0
-	mtctr   r3
-	lis     r5, 4
-
-tlblp:
-	tlbie   r3
-	sync
-	addi    r3, r3, 0x1000
-	cmplw   r3, r5
-	blt     tlblp
-
-	sync
-
-/*
- *  Enable Data Translation
- */
-	lis	r4, MEMORY_MGMT_MSR_BITS@h
-	ori	r4, r4, MEMORY_MGMT_MSR_BITS@l
-	mfmsr	r3
-	or	r3, r4, r3
-	mtmsr	r3
-	isync
-	sync
-
-	blr
-
-
-#ifdef USE_V2_INIT
-/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */
-/* Macro for hiadjust and lo */
-#define HIADJ(arg)	arg@ha
-#define HI(arg)		arg@h
-#define LO(arg)		arg@l
-
-#undef LOADPTR
-#define	LOADPTR(reg,const32) \
-	  addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)
-
-.globl  early_init_f
-
-early_init_f:
-/* MPC8245/BMW CPCI System Init
- * Jimmy Blair, Broadcom Corp, 2002.
- */
-	mflr    r11
-	/* Zero-out registers */
-
-	addis	r0,r0,0
-	mtspr	SPRG0,r0
-	mtspr	SPRG1,r0
-	mtspr	SPRG2,r0
-	mtspr	SPRG3,r0
-
-	/* Set MPU/MSR to a known state. Turn on FP */
-
-	LOADPTR (r3, MSR_FP)
-	sync
-	mtmsr	r3
-	isync
-
-	/* Init the floating point control/status register */
-
-	mtfsfi	7,0x0
-	mtfsfi	6,0x0
-	mtfsfi	5,0x0
-	mtfsfi	4,0x0
-	mtfsfi	3,0x0
-	mtfsfi	2,0x0
-	mtfsfi	1,0x0
-	mtfsfi	0,0x0
-	isync
-
-	/* Set MPU/MSR to a known state. Turn off FP */
-
-#if 1	/* Turn off floating point (remove to keep FP on) */
-	andi.	r3, r3, 0
-	sync
-	mtmsr	r3
-	isync
-#endif
-
-	/* Init the Segment registers */
-
-	andi.	r3, r3, 0
-	isync
-	mtsr	0,r3
-	isync
-	mtsr	1,r3
-	isync
-	mtsr	2,r3
-	isync
-	mtsr	3,r3
-	isync
-	mtsr	4,r3
-	isync
-	mtsr	5,r3
-	isync
-	mtsr	6,r3
-	isync
-	mtsr	7,r3
-	isync
-	mtsr	8,r3
-	isync
-	mtsr	9,r3
-	isync
-	mtsr	10,r3
-	isync
-	mtsr	11,r3
-	isync
-	mtsr	12,r3
-	isync
-	mtsr	13,r3
-	isync
-	mtsr	14,r3
-	isync
-	mtsr	15,r3
-	isync
-
-	/* Turn off data and instruction cache control bits */
-
-	mfspr	r3, HID0
-	isync
-	rlwinm	r4, r3, 0, 18, 15	/* r4 has ICE and DCE bits cleared */
-	sync
-	isync
-	mtspr	HID0, r4		/* HID0 = r4 */
-	isync
-
-	/* Get cpu type */
-
-	mfspr	r28, PVR
-	rlwinm	r28, r28, 16, 16, 31
-
-	/* invalidate the MPU's data/instruction caches */
-
-	lis	r3, 0x0
-	cmpli	0, 0, r28, CPU_TYPE_603
-	beq	cpuIs603
-	cmpli	0, 0, r28, CPU_TYPE_603E
-	beq	cpuIs603
-	cmpli	0, 0, r28, CPU_TYPE_603P
-	beq	cpuIs603
-	cmpli	0, 0, r28, CPU_TYPE_604R
-	bne	cpuNot604R
-
-cpuIs604R:
-	lis	r3, 0x0
-	mtspr	HID0, r3		/* disable the caches */
-	isync
-	ori	r4, r4, 0x0002		/* disable BTAC by setting bit 30 */
-
-cpuNot604R:
-	ori	r3, r3, (HID0_ICFI |HID0_DCI)
-
-cpuIs603:
-	ori	r3, r3, (HID0_ICE | HID0_DCE)
-	or	r4, r4, r3		/* set bits */
-	sync
-	isync
-	mtspr	HID0, r4		/* HID0 = r4 */
-	andc	r4, r4, r3		/* clear bits */
-	isync
-	cmpli	0, 0, r28, CPU_TYPE_604
-	beq	cpuIs604
-	cmpli	0, 0, r28, CPU_TYPE_604E
-	beq	cpuIs604
-	cmpli	0, 0, r28, CPU_TYPE_604R
-	beq	cpuIs604
-	mtspr	HID0, r4
-	isync
-
-#ifdef USER_I_CACHE_ENABLE
-	b	instCacheOn603
-#else
-	b	cacheEnableDone
-#endif
-
-cpuIs604:
-	LOADPTR (r5, 0x1000)		/* loop count, 0x1000 */
-	mtspr	CTR, r5
-loopDelay:
-	nop
-	bdnz	loopDelay
-	isync
-	mtspr	HID0, r4
-	isync
-
-	/* turn the Instruction cache ON for faster FLASH ROM boots */
-
-#ifdef USER_I_CACHE_ENABLE
-
-	ori	r4, r4, (HID0_ICE | HID0_ICFI)
-	isync				/* Synchronize for ICE enable */
-	b	writeReg4
-instCacheOn603:
-	ori	r4, r4, (HID0_ICE | HID0_ICFI)
-	rlwinm	r3, r4, 0, 21, 19	/* clear the ICFI bit */
-
-	/*
-	 * The setting of the instruction cache enable (ICE) bit must be
-	 * preceded by an isync instruction to prevent the cache from being
-	 * enabled or disabled while an instruction access is in progress.
-	 */
-	isync
-writeReg4:
-	mtspr	HID0, r4		/* Enable Instr Cache & Inval cache */
-	cmpli	0, 0, r28, CPU_TYPE_604
-	beq	cacheEnableDone
-	cmpli	0, 0, r28, CPU_TYPE_604E
-	beq	cacheEnableDone
-
-	mtspr	HID0, r3		/* using 2 consec instructions */
-					/* PPC603 recommendation */
-#endif
-cacheEnableDone:
-
-	/* Detect map A or B */
-
-	addis	r5,r0, HI(CHRP_REG_ADDR)
-	addis	r6,r0, HI(CHRP_REG_DATA)
-	LOADPTR (r7, KAHLUA_ID)		/* Kahlua PCI controller ID */
-	LOADPTR (r8, BMC_BASE)
-
-	stwbrx	r8,0,(r5)
-	lwbrx	r3,0,(r6)		/* Store read value to r3 */
-	cmp	0,0,r3,r7
-	beq	cr0, X4_KAHLUA_START
-
-	/* It's not an 8240, is it an 8245? */
-
-	LOADPTR (r7, KAHLUA2_ID)	/* Kahlua PCI controller ID */
-	cmp	0,0,r3,r7
-	beq	cr0, X4_KAHLUA_START
-
-	/* Save the PCI controller type in r7 */
-	mr	r7, r3
-
-	LOADPTR (r5, PREP_REG_ADDR)
-	LOADPTR (r6, PREP_REG_DATA)
-
-X4_KAHLUA_START:
-	/* MPC8245 changes begin here */
-	LOADPTR (r3, MPC107_PCI_CMD)	/* PCI command reg */
-	stwbrx	r3,0,r5
-	li	r4, 6			/* Command register value */
-	sthbrx	r4, 0, r6
-
-	LOADPTR (r3, MPC107_PCI_STAT)	/* PCI status reg */
-	stwbrx	r3,0,r5
-	li	r4, -1			/* Write-to-clear all bits */
-	li	r3, 2			/* PCI_STATUS is at +2 offset */
-	sthbrx	r4, r3, r6
-
-	/*-------PROC_INT1_ADR */
-
-	LOADPTR (r3, PROC_INT1_ADR)	/* Processor I/F Config 1 reg. */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0xff141b98)
-	stwbrx	r4,0,r6
-
-	/*-------PROC_INT2_ADR */
-
-	LOADPTR (r3, PROC_INT2_ADR)	/* Processor I/F Config 2 reg. */
-	stwbrx	r3,0,r5
-	lis	r4, 0x2000		/* Flush PCI config writes */
-	stwbrx	r4,0,r6
-
-	LOADPTR (r9, KAHLUA2_ID)
-	cmpl	0, 0, r7, r9
-	bne     L1not8245
-
-	/* MIOCR1 -- turn on bit for DLL delay */
-
-	LOADPTR (r3, MIOCR1_ADR_X)
-	stwbrx	r3,0,r5
-	li      r4, 0x04
-	stb	r4, MIOCR1_SHIFT(r6)
-
-	/* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
-	/* SDRAM_CLK_DEL (0x77)*/
-
-	LOADPTR (r3, MIOCR2_ADR_X)
-	stwbrx	r3,0,r5
-	li      r4, 0x10
-	stb	r4, MIOCR2_SHIFT(r6)
-
-	/* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
-
-	LOADPTR (r3, PMCR2_ADR_X)
-	stwbrx	r3,0,r5
-	li      r4, 0x20
-	stb	r4, PMCR2_SHIFT(r6)
-
-	/* Initialize EUMBBAR early since 8245 has internal UART in EUMB */
-
-	LOADPTR (r3, EUMBBAR)
-	stwbrx	r3,0,r5
-	LOADPTR (r4, CONFIG_SYS_EUMB_ADDR)
-	stwbrx	r4,0,r6
-
-L1not8245:
-
-	/* Toggle the DLL reset bit in AMBOR */
-
-	LOADPTR (r3, AMBOR)
-	stwbrx	r3,0,r5
-	lbz	r4, 0(r6)
-
-	andi.   r4, r4, 0xdf
-	stb	r4, 0(r6)		/* Clear DLL_RESET */
-	sync
-
-	ori     r4, r4, 0x20		/* Set DLL_RESET */
-	stb	r4, 0(r6)
-	sync
-
-	andi.   r4, r4, 0xdf
-	stb	r4, 0(r6)		/* Clear DLL_RESET */
-
-
-	/* Enable RCS2, use supplied timings */
-	LOADPTR (r3, ERCR1)
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0x80408000)
-	stwbrx	r4,0,r6
-
-	/* Disable RCS3 parameters */
-	LOADPTR (r3, ERCR2)
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0x00000000)
-	stwbrx	r4,0,r6
-
-	/* RCS3 at 0x70000000, 64KBytes */
-	LOADPTR (r3, ERCR2)
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0x00000004)
-	stwbrx	r4,0,r6
-
-	/*-------MCCR1 */
-
-#ifdef INCLUDE_ECC
-#define MC_ECC				1
-#else /* INCLUDE_ECC */
-#define MC_ECC				0
-#endif /* INCLUDE_ECC */
-
-#define MC1_ROMNAL			8		/* 0-15 */
-#define MC1_ROMFAL			11		/* 0-31 */
-#define MC1_DBUS_SIZE			0		/* 0-3, read only */
-#define MC1_BURST			0		/* 0-1 */
-#define MC1_MEMGO			0		/* 0-1 */
-#define MC1_SREN			1		/* 0-1 */
-#define MC1_RAM_TYPE			0		/* 0-1 */
-#define MC1_PCKEN			MC_ECC		/* 0-1 */
-#define MC1_BANKBITS			0x5555		/* 2 bits/bank 7-0 */
-
-	LOADPTR (r3, MEM_CONT1_ADR)	/* Set MCCR1 (F0) */
-	stwbrx	r3,0,r5
-	LOADPTR(r4, \
-		MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \
-		MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \
-		MC1_MEMGO << 19 | MC1_SREN << 18 | \
-		MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 )
-	li	r3, MC1_BANKBITS
-	cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
-	bne     BankBitsAdd
-	cmpli   0, 0, r3, 0x5555
-	beq     K2BankBitsHack		/* On 8245, 5555 ==> 0 */
-BankBitsAdd:
-	ori	r4, r3, 0
-K2BankBitsHack:
-	stwbrx	r4, 0, r6
-
-	/*------- MCCR2 */
-
-#define MC2_TS_WAIT_TIMER		0		/* 0-7 */
-#define MC2_ASRISE			8		/* 0-15 */
-#define MC2_ASFALL			4		/* 0-15 */
-#define MC2_INLINE_PAR_NOT_ECC		0		/* 0-1 */
-#define MC2_WRITE_PARITY_CHK_EN		MC_ECC		/* 0-1 */
-#define MC2_INLRD_PARECC_CHK_EN		MC_ECC		/* 0-1 */
-#define MC2_ECC_EN			0		/* 0-1 */
-#define MC2_EDO				0		/* 0-1 */
-/*
-*  N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM.
-*  May need to be decreased for 100 MHz
-*/
-#define MC2_REFINT			0x3a5		/* 0-0x3fff */
-#define MC2_RSV_PG			0		/* 0-1 */
-#define MC2_RMW_PAR			MC_ECC		/* 0-1 */
-
-	LOADPTR (r3, MEM_CONT2_ADR)	/* Set MCCR2 (F4) */
-	stwbrx	r3,0,r5
-	LOADPTR(r4, \
-		MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \
-		MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \
-		MC2_WRITE_PARITY_CHK_EN << 19 | \
-		MC2_INLRD_PARECC_CHK_EN << 18 | \
-		MC2_ECC_EN << 17 | MC2_EDO << 16 | \
-		MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
-	cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
-	bne     notK2
-	/* clear Kahlua2 reserved bits */
-	LOADPTR (r3, 0xfffcffff)
-	and	r4, r4, r3
-notK2:
-	stwbrx	r4,0,r6
-
-	/*------- MCCR3 */
-
-#define MC_BSTOPRE			0x079		/* 0-0x7ff */
-
-#define MC3_BSTOPRE_U			(MC_BSTOPRE >> 4 & 0xf)
-#define MC3_REFREC			8		/* 0-15 */
-#define MC3_RDLAT			(4+MC_ECC)	/* 0-15 */
-#define MC3_CPX				0		/* 0-1 */
-#define MC3_RAS6P			0		/* 0-15 */
-#define MC3_CAS5			0		/* 0-7 */
-#define MC3_CP4				0		/* 0-7 */
-#define MC3_CAS3			0		/* 0-7 */
-#define MC3_RCD2			0		/* 0-7 */
-#define MC3_RP1				0		/* 0-7 */
-
-	LOADPTR (r3, MEM_CONT3_ADR)	/* Set MCCR3 (F8) */
-	stwbrx	r3,0,r5
-	LOADPTR(r4, \
-		MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \
-		MC3_RDLAT << 20 | MC3_CPX << 19 | \
-		MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
-		MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
-	cmpl	0, 0, r7, r9              /* Check for Kahlua2 */
-	bne     notK2b
-	/* clear Kahlua2 reserved bits */
-	LOADPTR (r3, 0xff000000)
-	and	r4, r4, r3
-notK2b:
-	stwbrx	r4,0,r6
-
-	/*------- MCCR4 */
-
-#define MC4_PRETOACT			3		/* 0-15 */
-#define MC4_ACTOPRE			5		/* 0-15 */
-#define MC4_WMODE			0		/* 0-1 */
-#define MC4_INLINE			MC_ECC		/* 0-1 */
-#define MC4_REGISTERED			(1-MC_ECC)	/* 0-1 */
-#define MC4_BSTOPRE_UU			(MC_BSTOPRE >> 8 & 3)
-#define MC4_REGDIMM			0		/* 0-1 */
-#define MC4_SDMODE_CAS			2		/* 0-7 */
-#define MC4_DBUS_RCS1			1		/* 0-1, 8-bit */
-#define MC4_SDMODE_WRAP			0		/* 0-1 */
-#define MC4_SDMODE_BURST		2		/* 0-7 */
-#define MC4_ACTORW			3		/* 0-15 */
-#define MC4_BSTOPRE_L			(MC_BSTOPRE & 0xf)
-
-	LOADPTR (r3, MEM_CONT4_ADR)	/* Set MCCR4 (FC) */
-	stwbrx	r3,0,r5
-	LOADPTR(r4, \
-		MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \
-		MC4_WMODE << 23 | MC4_INLINE << 22 | \
-		MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \
-		MC4_DBUS_RCS1 << 17 | \
-		MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
-		MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
-		MC4_ACTORW << 4 | MC4_BSTOPRE_L)
-	cmpl	0, 0, r7, r9                /* Check for Kahlua 2 */
-	bne     notK2c
-	/* Turn on Kahlua2 extended ROM space */
-	LOADPTR (r3, 0x00200000)
-	or	r4, r4, r3
-notK2c:
-	stwbrx	r4,0,r6
-
-#ifdef INCLUDE_ECC
-	/*------- MEM_ERREN1 */
-
-	LOADPTR (r3, MEM_ERREN1_ADR)	/* Set MEM_ERREN1 (c0) */
-	stwbrx	r3,0,r5
-	lwbrx	r4,0,r6
-	ori	r4,r4,4			/* Set MEM_PERR_EN */
-	stwbrx	r4,0,r6
-#endif /* INCLUDE_ECC */
-
-	/*------- MSAR/MEAR */
-
-	LOADPTR (r3, MEM_START1_ADR)	/* Set MSAR1 (80) */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0xc0804000)
-	stwbrx	r4,0,r6
-
-	LOADPTR (r3, MEM_START2_ADR)	/* Set MSAR2 (84) */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0xc0804000)
-	stwbrx	r4,0,r6
-
-	LOADPTR (r3, XMEM_START1_ADR)	/* Set MESAR1 (88) */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0x00000000)
-	stwbrx	r4,0,r6
-
-	LOADPTR (r3, XMEM_START2_ADR)	/* Set MESAR2 (8c) */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0x01010101)
-	stwbrx	r4,0,r6
-
-	LOADPTR (r3, MEM_END1_ADR)	/* Set MEAR1 (90) */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0xffbf7f3f)
-	stwbrx	r4,0,r6
-
-	LOADPTR (r3, MEM_END2_ADR)	/* Set MEAR2 (94) */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0xffbf7f3f)
-	stwbrx	r4,0,r6
-
-	LOADPTR (r3, XMEM_END1_ADR)	/* MEEAR1 (98) */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0x00000000)
-	stwbrx	r4,0,r6
-
-	LOADPTR (r3, XMEM_END2_ADR)	/* MEEAR2 (9c) */
-	stwbrx	r3,0,r5
-	LOADPTR (r4, 0x01010101)
-	stwbrx	r4,0,r6
-
-	/*-------ODCR */
-
-	LOADPTR (r3, ODCR_ADR_X)	/* Set ODCR */
-	stwbrx	r3,0,r5
-
-	li	r4, 0x7f
-	stb	r4, ODCR_SHIFT(r6)	/* ODCR is at +3 offset */
-
-	/*-------MBEN */
-
-	LOADPTR (r3, MEM_EN_ADR)	/* Set MBEN (a0) */
-	stwbrx	r3,0,r5
-	li	r4, 0x01		/* Enable bank 0 */
-	stb	r4, 0(r6)		/* MBEN is at +0 offset */
-
-#if 0   /* Jimmy:  I think page made is broken */
-	/*-------PGMAX */
-
-	LOADPTR (r3, MPM_ADR_X)
-	stwbrx	r3,0,r5
-	li	r4, 0x32
-	stb	r4, MPM_SHIFT(r6)		/* PAGE_MODE is at +3 offset */
-#endif
-
-	/* Wait before initializing other registers */
-
-	lis	r4,0x0001
-	mtctr	r4
-
-KahluaX4wait200us:
-	bdnz	KahluaX4wait200us
-
-	/* Set MEMGO bit */
-
-	LOADPTR (r3, MEM_CONT1_ADR)	/* MCCR1 (F0) |= PGMAX */
-	stwbrx	r3,0,r5
-	lwbrx	r4,0,r6			/* old MCCR1 */
-	oris	r4,r4,0x0008		/* MEMGO=1 */
-	stwbrx	r4, 0, r6
-
-	/* Wait again */
-
-	addis	r4,r0,0x0002
-	ori	r4,r4,0xffff
-
-	mtctr	r4
-
-KahluaX4wait8ref:
-	bdnz	KahluaX4wait8ref
-
-	sync
-	eieio
-	mtlr    r11
-	blr
-
-#else /* USE_V2_INIT */
-
-
-/* U-Boot works, but memory will not run reliably for all address ranges.
- * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not
- * initialized correctly. Could work if debugged.
- */
-/* PCI Support routines */
-
-    .globl __pci_config_read_32
-__pci_config_read_32:
-    lis     r4, 0xfec0
-    stwbrx   r3, r0, r4
-    sync
-    lis     r4, 0xfee0
-    lwbrx   r3, 0, r4
-    blr
-    .globl __pci_config_read_16
-__pci_config_read_16:
-    lis     r4, 0xfec0
-    andi.    r5, r3, 2
-    stwbrx  r3, r0, r4
-    sync
-    oris     r4, r5, 0xfee0
-    lhbrx    r3, r0, r4
-    blr
-    .globl __pci_config_read_8
-__pci_config_read_8:
-    lis     r4, 0xfec0
-    andi.    r5, r3, 3
-    stwbrx  r3, r0, r4
-    sync
-    oris     r4, r5, 0xfee0
-    lbz      r3, 0(4)
-    blr
-    .globl __pci_config_write_32
-__pci_config_write_32:
-    lis     r5, 0xfec0
-    stwbrx   r3, r0, r5
-    sync
-    lis      r5, 0xfee0
-    stwbrx   r4, r0, r5
-    sync
-    blr
-    .globl __pci_config_write_16
-__pci_config_write_16:
-    lis     r5, 0xfec0
-    andi.    r6, r3, 2
-    stwbrx  r3, r0, 5
-    sync
-    oris     r5, r6, 0xfee0
-    sthbrx    r4, r0, r5
-    sync
-    blr
-    .globl __pci_config_write_8
-__pci_config_write_8:
-    lis      r5, 0xfec0
-    andi.    r6, r3, 3
-    stwbrx   r3, r0, r5
-    sync
-    oris      r5, r6, 0xfee0
-    stb       r4, 0(r5)
-    sync
-    blr
-    .globl  in_8
-in_8:
-    oris    r3, r3, 0xfe00
-    lbz     r3,0(r3)
-    blr
-    .globl  in_16
-in_16:
-    oris    r3, r3, 0xfe00
-    lhbrx   r3, 0, r3
-    blr
-    .globl in_16_ne
-in_16_ne:
-    oris    r3, r3, 0xfe00
-    lhzx    r3, 0, r3
-    blr
-    .globl  in_32
-in_32:
-    oris    r3, r3, 0xfe00
-    lwbrx   r3, 0, r3
-    blr
-    .globl  out_8
-out_8:
-    oris    r3, r3, 0xfe00
-    stb     r4, 0(r3)
-    eieio
-    blr
-    .globl  out_16
-out_16:
-    oris    r3, r3, 0xfe00
-    sthbrx  r4, 0, r3
-    eieio
-    blr
-    .globl  out_16_ne
-out_16_ne:
-    oris    r3, r3, 0xfe00
-    sth     r4, 0(r3)
-    eieio
-    blr
-    .globl  out_32
-out_32:
-    oris    r3, r3, 0xfe00
-    stwbrx  r4, 0, r3
-    eieio
-    blr
-    .globl  read_8
-read_8:
-    lbz     r3,0(r3)
-    blr
-    .globl  read_16
-read_16:
-    lhbrx   r3, 0, r3
-    blr
-    .globl  read_32
-read_32:
-    lwbrx   r3, 0, r3
-    blr
-    .globl  read_32_ne
-read_32_ne:
-    lwz     r3, 0(r3)
-    blr
-    .globl  write_8
-write_8:
-    stb     r4, 0(r3)
-    eieio
-    blr
-    .globl  write_16
-write_16:
-    sthbrx  r4, 0, r3
-    eieio
-    blr
-    .globl  write_32
-write_32:
-    stwbrx  r4, 0, r3
-    eieio
-    blr
-    .globl  write_32_ne
-write_32_ne:
-    stw     r4, 0(r3)
-    eieio
-    blr
-
-
-.globl  early_init_f
-
-early_init_f:
-	mflr    r11
-	lis     r10, 0x8000
-
-	/* PCI Latency Timer */
-	li      r4, 0x0d
-	ori     r3, r10, PLTR@l
-	bl      __pci_config_write_8
-
-	/* Cache Line Size */
-	li      r4, 0x08
-	ori     r3, r10, PCLSR@l
-	bl      __pci_config_write_8
-
-	/* PCI Cmd */
-	li      r4, 6
-	ori     r3, r10, PCICR@l
-	bl      __pci_config_write_16
-
-#if 1
-	/* PCI Stat */
-	ori     r3, r10, PCISR@l
-	bl      __pci_config_read_16
-	ori     r4, r4, 0xffff
-	ori     r3, r10, PCISR@l
-	bl      __pci_config_write_16
-#endif
-
-	/* PICR1 */
-	lis     r4, 0xff14
-	ori     r4, r4, 0x1b98
-	ori     r3, r10, PICR1@l
-	bl      __pci_config_write_32
-
-
-	/* PICR2 */
-	lis     r4, 0x0404
-	ori     r4, r4, 0x0004
-	ori     r3, r10, PICR2@l
-	bl      __pci_config_write_32
-
-	/* MIOCR1 */
-	li      r4, 0x04
-	ori     r3, r10, MIOCR1@l
-	bl      __pci_config_write_8
-
-	/* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
-	/* SDRAM_CLK_DEL (0x77)*/
-	li      r4, 0x10
-	ori     r3, r10, MIOCR2@l
-	bl      __pci_config_write_8
-
-	/* EUMBBAR */
-	lis     r4, 0xfc00
-	ori     r3, r10, EUMBBAR@l
-	bl      __pci_config_write_32
-
-	/* AMBOR */
-
-       /* Even if Address Map B is not being used (though it should),
-	* the memory DLL needs to be cleared/set/cleared before using memory.
-	*/
-
-	ori     r3, r10, AMBOR@l
-	bl      __pci_config_read_8	/* get Current bits */
-
-	andi.   r4, r4, 0xffdf
-	ori     r3, r10, AMBOR@l
-	bl      __pci_config_write_16	/* Clear DLL_RESET */
-
-	ori    r4, r4, 0x0020
-	ori     r3, r10, AMBOR@l
-	bl      __pci_config_write_16	/* Set DLL_RESET */
-
-	andi.   r4, r4, 0xffdf
-	ori     r3, r10, AMBOR@l
-	bl      __pci_config_write_16	/* Clear DLL_RESET */
-
-	/* ERCR1 */
-	lis     r4, 0x8040		/* Enable RCS2, use supplied timings */
-	ori     r4, r4, 0x8000
-	ori     r3, r10, ERCR1@l
-	bl      __pci_config_write_32
-
-	/* ERCR2 */
-	lis     r4, 0x0000		/* Disable RCS3 parms */
-	ori     r4, r4, 0x0000
-	ori     r3, r10, ERCR2@l
-	bl      __pci_config_write_32
-
-	/* ERCR3 */
-	lis     r4, 0x0000		/* RCS3 at 0x70000000, 64K bytes */
-	ori     r4, r4, 0x0004
-	ori     r3, r10, ERCR2@l
-	bl      __pci_config_write_32
-
-	/* Preserve memgo bit */
-	/* MCCR1 */
-
-/*	lis     r4, 0x75a8		/  Safe Local ROM = 11+3 clocks */
-	lis     r4, 0x75a0              /* Safe Local ROM = 11+3 clocks */
-/*      lis     r4, 0x73a0              /  Fast Local ROM = 7+3 clocks */
-/*      oris    r4, r4, 0x0010          /  Burst ROM/Flash enable */
-/*      oris    r4, r4, 0x0004          /  Self-refresh enable */
-
-/*      ori     r4,r4,0xFFFF            /  16Mbit  2bank SDRAM */
-/*      ori     r4,r4,0xAAAA            /  256Mbit 4bank SDRAM (8245 only) */
-/*      ori     r4,r4,0x5555            /  64Mbit  2bank SDRAM */
-	ori     r4,r4,0x0000            /* 64Mbit  4bank SDRAM */
-
-	ori     r3, r10, MCCR1@l
-	bl      __pci_config_write_32
-
-	/* MCCR2 */
-
-	lis     r4,0x0000
-/*      oris    r4,r4,0x4000            /  TS_WAIT_TIMER = 3 clocks */
-	oris    r4,r4,0x1000            /* ASRISE = 8 clocks */
-	oris    r4,r4,0x0080            /* ASFALL = 8 clocks */
-/*      oris    r4,r4,0x0010            /  SDRAM Parity (else ECC) */
-/*      oris    r4,r4,0x0008            /  Write parity check */
-/*      oris    r4,r4,0x0004            /  SDRAM inline reads */
-
-
-/* Select a refresh rate; it needs to match the bus speed; if too */
-/* slow, data may be lost; if too fast, performance is lost.  We */
-/* use the fastest value so we run at all speeds. */
-/* Refresh = (15600ns/busclk) - (213 (see UM)). */
-
-/*      ori     r4,r4,0x1d2c            /  133 MHz mem bus        = 1867 */
-/*      ori     r4,r4,0x150c            /  100 MHz mem bus        = 1347 */
-/*      ori     r4,r4,0x10fc            /   83 MHz mem bus        = 1087 */
-/*      ori     r4,r4,0x0cc4            /   66 MHz mem bus        =  817 */
-	ori     r4,r4,0x04cc            /*  33 MHz mem bus (SAFE) =  307 */
-/*      ori     r4,r4,0x0002            /  Reserve a page */
-/*      ori     r4,r4,0x0001            /  RWM parity */
-
-	ori     r3, r10, MCCR2@l
-	bl      __pci_config_write_32
-
-
-	/* MCCR3 */
-	lis     r4,0x0000               /* BSTOPRE_M = 7 (see A/N) */
-	oris    r4,r4,0x0500            /* REFREC    = 8 clocks */
-	ori     r3, r10, MCCR3@l
-	bl      __pci_config_write_32
-
-	/* MCCR4 */                     /* Turn on registered buffer mode */
-	lis     r4, 0x2000              /* PRETOACT = 3 clocks */
-	oris    r4,r4,0x0400            /* ACTOPRE  = 5 clocks */
-/*      oris    r4,r4,0x0080            /  Enable 8-beat burst (32-bit bus) */
-/*      oris    r4,r4,0x0040            /  Enable Inline ECC/Parity */
-	oris    r4,r4,0x0020            /* EXTROM enabled */
-	oris    r4,r4,0x0010            /* Registered buffers */
-/*      oris    r4,r4,0x0000            /  BSTOPRE_U = 0 (see A/N) */
-	oris    r4,r4,0x0002            /* DBUS_SIZ[2] (8 bit on RCS1) */
-
-/*      ori     r4,r4,0x8000            /  Registered DIMMs */
-	ori     r4,r4,0x2000            /*CAS Latency (CL=3) (see RDLAT) */
-/*      ori     r4,r4,0x2000            /  CAS Latency (CL=2) (see RDLAT) */
-/*      ori     r4,r4,0x0300            /  Sequential wrap/8-beat burst */
-	ori     r4,r4,0x0200            /* Sequential wrap/4-beat burst */
-	ori     r4,r4,0x0030            /* ACTORW  = 3 clocks */
-	ori     r4,r4,0x0009            /* BSTOPRE_L = 9 (see A/N) */
-
-	ori     r3, r10, MCCR4@l
-	bl      __pci_config_write_32
-
-	/* MSAR1 */
-	lis     r4, 0xc0804000@h
-	ori     r4, r4, 0xc0804000@l
-	ori     r3, r10, MSAR1@l
-	bl      __pci_config_write_32
-
-	/* MSAR2 */
-	lis     r4, 0xc0804000@h
-	ori     r4, r4, 0xc0804000@l
-	ori     r3, r10, MSAR2@l
-	bl      __pci_config_write_32
-
-	/* MESAR1 */
-	lis     r4, 0x00000000@h
-	ori     r4, r4, 0x00000000@l
-	ori     r3, r10, EMSAR1@l
-	bl      __pci_config_write_32
-
-	/* MESAR2 */
-	lis     r4, 0x01010101@h
-	ori     r4, r4, 0x01010101@l
-	ori     r3, r10, EMSAR2@l
-	bl      __pci_config_write_32
-
-	/* MEAR1 */
-	lis     r4, 0xffbf7f3f@h
-	ori     r4, r4, 0xffbf7f3f@l
-	ori     r3, r10, MEAR1@l
-	bl      __pci_config_write_32
-
-	/* MEAR2 */
-	lis     r4, 0xffbf7f3f@h
-	ori     r4, r4, 0xffbf7f3f@l
-	ori     r3, r10, MEAR2@l
-	bl      __pci_config_write_32
-
-	/* MEEAR1 */
-	lis     r4, 0x00000000@h
-	ori     r4, r4, 0x00000000@l
-	ori     r3, r10, EMEAR1@l
-	bl      __pci_config_write_32
-
-	/* MEEAR2 */
-	lis     r4, 0x01010101@h
-	ori     r4, r4, 0x01010101@l
-	ori     r3, r10, EMEAR2@l
-	bl      __pci_config_write_32
-
-	/* ODCR */
-	li      r4, 0x7f
-	ori     r3, r10, ODCR@l
-	bl      __pci_config_write_8
-
-	/* MBER */
-	li      r4, 0x01
-	ori     r3, r10, MBER@l
-	bl      __pci_config_write_8
-
-	/* Page CTR aka PGMAX */
-	li      r4, 0x32
-	ori     r3, r10, 0x70
-	bl      __pci_config_write_8
-
-#if 0
-	/* CLK Drive */
-	ori     r4, r10, 0xfc01 /* Top bit will be ignored */
-	ori     r3, r10, 0x74
-	bl      __pci_config_write_16
-#endif
-
-	/* delay */
-	lis     r7, 1
-	mtctr   r7
-label1:	bdnz    label1
-
-	/* Set memgo bit */
-	/* MCCR1 */
-	ori     r3, r10, MCCR1@l
-	bl      __pci_config_read_32
-	lis	r7, 0x0008
-	or	r4, r3, r7
-	ori     r3, r10, MCCR1@l
-	bl      __pci_config_write_32
-
-	/* delay again */
-	lis     r7, 1
-	mtctr   r7
-label2:	bdnz    label2
-#if 0
-/* DEBUG: Infinite loop, write then read */
-loop:
-	lis     r7, 0xffff
-	mtctr   r7
-	li	r3, 0x5004
-	lis	r4, 0xa0a0
-	ori	r4, r4, 0x5050
-	bl write_32_ne
-	li	r3, 0x5004
-	bl read_32_ne
-	bdnz    loop
-#endif
-	mtlr    r11
-	blr
-#endif
diff --git a/board/bmw/flash.c b/board/bmw/flash.c
deleted file mode 100644
index 57ffe08..0000000
--- a/board/bmw/flash.c
+++ /dev/null
@@ -1,779 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-
-#define ROM_CS0_START	0xFF800000
-#define ROM_CS1_START	0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t * info);
-#endif /* 0 */
-
-/*flash command address offsets*/
-
-#if 0
-#define ADDR0           (0x555)
-#define ADDR1           (0x2AA)
-#define ADDR3           (0x001)
-#else
-#define ADDR0		(0xAAA)
-#define ADDR1		(0x555)
-#define ADDR3		(0x001)
-#endif
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-#if 0
-static int byte_parity_odd (unsigned char x) __attribute__ ((const));
-#endif /* 0 */
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-	__attribute__ ((const));
-
-typedef struct {
-	FLASH_WORD_SIZE extval;
-	unsigned short intval;
-} map_entry;
-
-#if 0
-static int byte_parity_odd (unsigned char x)
-{
-	x ^= x >> 4;
-	x ^= x >> 2;
-	x ^= x >> 1;
-	return (x & 0x1) != 0;
-}
-#endif /* 0 */
-
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-{
-	static const map_entry mfct_map[] = {
-		{(FLASH_WORD_SIZE) AMD_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
-		{(FLASH_WORD_SIZE) FUJ_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
-		{(FLASH_WORD_SIZE) STM_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
-		{(FLASH_WORD_SIZE) MT_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
-		{(FLASH_WORD_SIZE) INTEL_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
-		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
-		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
-	};
-
-	static const map_entry chip_map[] = {
-		{AMD_ID_F040B, FLASH_AM040},
-		{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
-	};
-
-	const map_entry *p;
-	unsigned long result = FLASH_UNKNOWN;
-
-	/* find chip id */
-	for (p = &chip_map[0];
-	     p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
-		if (p->extval == chip) {
-			result = FLASH_VENDMASK | p->intval;
-			break;
-		}
-
-	/* find vendor id */
-	for (p = &mfct_map[0];
-	     p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
-		if (p->extval == mfct) {
-			result &= ~FLASH_VENDMASK;
-			result |= (unsigned long) p->intval << 16;
-			break;
-		}
-
-	return result;
-}
-
-
-unsigned long flash_init (void)
-{
-	unsigned long i;
-	unsigned char j;
-	static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		flash_info_t *const pflinfo = &flash_info[i];
-
-		pflinfo->flash_id = FLASH_UNKNOWN;
-		pflinfo->size = 0;
-		pflinfo->sector_count = 0;
-	}
-
-	for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
-		flash_info_t *const pflinfo = &flash_info[i];
-		const unsigned long base_address = flash_banks[i];
-		volatile FLASH_WORD_SIZE *const flash =
-			(FLASH_WORD_SIZE *) base_address;
-#if 0
-		volatile FLASH_WORD_SIZE *addr2;
-#endif
-#if 0
-		/* write autoselect sequence */
-		flash[0x5555] = 0xaa;
-		flash[0x2aaa] = 0x55;
-		flash[0x5555] = 0x90;
-#else
-		flash[0xAAA << (3 * i)] = 0xaa;
-		flash[0x555 << (3 * i)] = 0x55;
-		flash[0xAAA << (3 * i)] = 0x90;
-#endif
-		__asm__ __volatile__ ("sync");
-
-#if 0
-		pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]);
-#else
-		pflinfo->flash_id =
-			flash_id (flash[0x0], flash[0x2 + 14 * i]);
-#endif
-
-		switch (pflinfo->flash_id & FLASH_TYPEMASK) {
-		case FLASH_AM040:
-			pflinfo->size = 0x00080000;
-			pflinfo->sector_count = 8;
-			for (j = 0; j < 8; j++) {
-				pflinfo->start[j] =
-					base_address + 0x00010000 * j;
-				pflinfo->protect[j] = flash[(j << 16) | 0x2];
-			}
-			break;
-		case FLASH_STM800AB:
-			pflinfo->size = 0x00100000;
-			pflinfo->sector_count = 19;
-			pflinfo->start[0] = base_address;
-			pflinfo->start[1] = base_address + 0x4000;
-			pflinfo->start[2] = base_address + 0x6000;
-			pflinfo->start[3] = base_address + 0x8000;
-			for (j = 1; j < 16; j++) {
-				pflinfo->start[j + 3] =
-					base_address + 0x00010000 * j;
-			}
-#if 0
-			/* check for protected sectors */
-			for (j = 0; j < pflinfo->sector_count; j++) {
-				/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-				/* D0 = 1 if protected */
-				addr2 = (volatile FLASH_WORD_SIZE
-					 *) (pflinfo->start[j]);
-				if (pflinfo->flash_id & FLASH_MAN_SST)
-					pflinfo->protect[j] = 0;
-				else
-					pflinfo->protect[j] = addr2[2] & 1;
-			}
-#endif
-			break;
-		}
-		/* Protect monitor and environment sectors
-		 */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		flash_protect (FLAG_PROTECT_SET,
-			       CONFIG_SYS_MONITOR_BASE,
-			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-			       &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-		flash_protect (FLAG_PROTECT_SET,
-			       CONFIG_ENV_ADDR,
-			       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-			       &flash_info[0]);
-#endif
-
-		/* reset device to read mode */
-		flash[0x0000] = 0xf0;
-		__asm__ __volatile__ ("sync");
-	}
-
-	return flash_info[0].size + flash_info[1].size;
-}
-
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_MAN_SST) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type    */
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	} else {
-		/* set sector offsets for top boot block type       */
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	}
-
-}
-#endif /* 0 */
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	static const char unk[] = "Unknown";
-	const char *mfct = unk, *type = unk;
-	unsigned int i;
-
-	if (info->flash_id != FLASH_UNKNOWN) {
-		switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			mfct = "AMD";
-			break;
-		case FLASH_MAN_FUJ:
-			mfct = "FUJITSU";
-			break;
-		case FLASH_MAN_STM:
-			mfct = "STM";
-			break;
-		case FLASH_MAN_SST:
-			mfct = "SST";
-			break;
-		case FLASH_MAN_BM:
-			mfct = "Bright Microelectonics";
-			break;
-		case FLASH_MAN_INTEL:
-			mfct = "Intel";
-			break;
-		}
-
-		switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_AM040:
-			type = "AM29F040B (512K * 8, uniform sector size)";
-			break;
-		case FLASH_AM400B:
-			type = "AM29LV400B (4 Mbit, bottom boot sect)";
-			break;
-		case FLASH_AM400T:
-			type = "AM29LV400T (4 Mbit, top boot sector)";
-			break;
-		case FLASH_AM800B:
-			type = "AM29LV800B (8 Mbit, bottom boot sect)";
-			break;
-		case FLASH_AM800T:
-			type = "AM29LV800T (8 Mbit, top boot sector)";
-			break;
-		case FLASH_AM160T:
-			type = "AM29LV160T (16 Mbit, top boot sector)";
-			break;
-		case FLASH_AM320B:
-			type = "AM29LV320B (32 Mbit, bottom boot sect)";
-			break;
-		case FLASH_AM320T:
-			type = "AM29LV320T (32 Mbit, top boot sector)";
-			break;
-		case FLASH_STM800AB:
-			type = "M29W800AB (8 Mbit, bottom boot sect)";
-			break;
-		case FLASH_SST800A:
-			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
-			break;
-		case FLASH_SST160A:
-			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
-			break;
-		}
-	}
-
-	printf ("\n  Brand: %s Type: %s\n"
-		"  Size: %lu KB in %d Sectors\n",
-		mfct, type, info->size >> 10, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-
-	for (i = 0; i < info->sector_count; i++) {
-		unsigned long size;
-		unsigned int erased;
-		unsigned long *flash = (unsigned long *) info->start[i];
-
-		/*
-		 * Check if whole sector is erased
-		 */
-		size = (i != (info->sector_count - 1)) ?
-			(info->start[i + 1] - info->start[i]) >> 2 :
-			(info->start[0] + info->size - info->start[i]) >> 2;
-
-		for (flash = (unsigned long *) info->start[i], erased = 1;
-		     (flash != (unsigned long *) info->start[i] + size)
-		     && erased; flash++)
-			erased = *flash == ~0x0UL;
-
-		printf ("%s %08lX %s %s",
-			(i % 5) ? "" : "\n   ",
-			info->start[i],
-			erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
-	}
-
-	puts ("\n");
-	return;
-}
-
-#if 0
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
-	short i;
-	FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
-	printf ("flash_get_size: \n");
-	/* Write auto select command: read Manufacturer ID */
-	eieio ();
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA;
-	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55;
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90;
-	value = addr2[0];
-
-	switch (value) {
-	case (FLASH_WORD_SIZE) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case (FLASH_WORD_SIZE) SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);	/* no or unknown flash  */
-	}
-	printf ("recognised manufacturer");
-
-	value = addr2[ADDR3];	/* device ID        */
-	debug ("\ndev_code=%x\n", value);
-
-	switch (value) {
-	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;		/* => 0.5 MB        */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;		/* => 0.5 MB        */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;		/* => 1 MB      */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;		/* => 1 MB      */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;		/* => 2 MB      */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;		/* => 2 MB      */
-
-	case (FLASH_WORD_SIZE) SST_ID_xF800A:
-		info->flash_id += FLASH_SST800A;
-		info->sector_count = 16;
-		info->size = 0x00100000;
-		break;		/* => 1 MB      */
-
-	case (FLASH_WORD_SIZE) SST_ID_xF160A:
-		info->flash_id += FLASH_SST160A;
-		info->sector_count = 32;
-		info->size = 0x00200000;
-		break;		/* => 2 MB      */
-
-	case (FLASH_WORD_SIZE) AMD_ID_F040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x00080000;
-		break;		/* => 0.5 MB      */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);	/* => no or unknown flash */
-
-	}
-
-	printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id,
-		info->sector_count, info->size);
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_MAN_SST) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type    */
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	} else {
-		/* set sector offsets for top boot block type       */
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
-		if (info->flash_id & FLASH_MAN_SST)
-			info->protect[i] = 0;
-		else
-			info->protect[i] = addr2[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (FLASH_WORD_SIZE *) info->start[0];
-		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-#endif
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-	unsigned char sh8b;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Check the ROM CS */
-	if ((info->start[0] >= ROM_CS1_START)
-	    && (info->start[0] < ROM_CS0_START))
-		sh8b = 3;
-	else
-		sh8b = 0;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
-	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
-	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
-	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->
-								       start
-								       [sect]
-								       -
-								       info->
-								       start
-								       [0]) <<
-								      sh8b));
-			if (info->flash_id & FLASH_MAN_SST) {
-				addr[ADDR0 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00550055;
-				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				udelay (30000);	/* wait 30 ms */
-			} else
-				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last = start;
-	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
-						       info->
-						       start[0]) << sh8b));
-	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
-	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			serial_putc ('.');
-			last = now;
-		}
-	}
-
-      DONE:
-	/* reset to read mode */
-	addr = (FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
-	volatile FLASH_WORD_SIZE *dest2;
-	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
-	ulong start;
-	int flag;
-	int i;
-	unsigned char sh8b;
-
-	/* Check the ROM CS */
-	if ((info->start[0] >= ROM_CS1_START)
-	    && (info->start[0] < ROM_CS0_START))
-		sh8b = 3;
-	else
-		sh8b = 0;
-
-	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
-				     info->start[0]);
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
-		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i << sh8b] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts ();
-
-		/* data polling for D7 */
-		start = get_timer (0);
-		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c
deleted file mode 100644
index 4e83b90..0000000
--- a/board/bmw/m48t59y.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
- *
- * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and
- * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD)
- * registers which are used to set/get the internal date/time functions.
- *
- * This module implements Y2K compliance by taking full year numbers
- * and translating back and forth from the TOD 2-digit year.
- *
- * NOTE: for proper interaction with an operating system, the TOD should
- * be used to store Universal Coordinated Time (GMT) and timezone
- * conversions should be used.
- *
- * Here is a diagram of the memory layout:
- *
- * +---------------------------------------------+ 0xffe0a000
- * | Non-volatile memory                         | .
- * |                                             | .
- * | (8176 bytes of Non-volatile memory)         | .
- * |                                             | .
- * +---------------------------------------------+ 0xffe0bff0
- * | Flags                                       |
- * +---------------------------------------------+ 0xffe0bff1
- * | Unused                                      |
- * +---------------------------------------------+ 0xffe0bff2
- * | Alarm Seconds                               |
- * +---------------------------------------------+ 0xffe0bff3
- * | Alarm Minutes                               |
- * +---------------------------------------------+ 0xffe0bff4
- * | Alarm Date                                  |
- * +---------------------------------------------+ 0xffe0bff5
- * | Interrupts                                  |
- * +---------------------------------------------+ 0xffe0bff6
- * | WatchDog                                    |
- * +---------------------------------------------+ 0xffe0bff7
- * | Calibration                                 |
- * +---------------------------------------------+ 0xffe0bff8
- * | Seconds                                     |
- * +---------------------------------------------+ 0xffe0bff9
- * | Minutes                                     |
- * +---------------------------------------------+ 0xffe0bffa
- * | Hours                                       |
- * +---------------------------------------------+ 0xffe0bffb
- * | Day                                         |
- * +---------------------------------------------+ 0xffe0bffc
- * | Date                                        |
- * +---------------------------------------------+ 0xffe0bffd
- * | Month                                       |
- * +---------------------------------------------+ 0xffe0bffe
- * | Year (2 digits only)                        |
- * +---------------------------------------------+ 0xffe0bfff
- */
-#include <common.h>
-#include <rtc.h>
-#include "bmw.h"
-
-/*
- * Imported from mousse.h:
- *
- *   TOD_REG_BASE		Base of m48t59y TOD registers
- *   SYS_TOD_UNPROTECT()	Disable NVRAM write protect
- *   SYS_TOD_PROTECT()		Re-enable NVRAM write protect
- */
-
-#define YEAR		0xf
-#define MONTH		0xe
-#define DAY		0xd
-#define DAY_OF_WEEK	0xc
-#define HOUR		0xb
-#define MINUTE		0xa
-#define SECOND		0x9
-#define CONTROL		0x8
-#define WATCH		0x7
-#define INTCTL		0x6
-#define WD_DATE		0x5
-#define WD_HOUR		0x4
-#define WD_MIN		0x3
-#define WD_SEC		0x2
-#define _UNUSED		0x1
-#define FLAGS		0x0
-
-#define M48_ADDR	((volatile unsigned char *) TOD_REG_BASE)
-
-int m48_tod_init(void)
-{
-    SYS_TOD_UNPROTECT();
-
-    M48_ADDR[CONTROL] = 0;
-    M48_ADDR[WATCH] = 0;
-    M48_ADDR[INTCTL] = 0;
-
-    /*
-     * If the oscillator is currently stopped (as on a new part shipped
-     * from the factory), start it running.
-     *
-     * Here is an example of the TOD bytes on a brand new M48T59Y part:
-     *		00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01
-     */
-
-    if (M48_ADDR[SECOND] & 0x80)
-	M48_ADDR[SECOND] = 0;
-
-    /* Is battery low */
-    if ( M48_ADDR[FLAGS] & 0x10) {
-	 printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n");
-    }
-
-    SYS_TOD_PROTECT();
-
-    return 0;
-}
-
-/*
- * m48_tod_set
- */
-
-static int to_bcd(int value)
-{
-    return value / 10 * 16 + value % 10;
-}
-
-static int from_bcd(int value)
-{
-    return value / 16 * 10 + value % 16;
-}
-
-static int day_of_week(int y, int m, int d)	/* 0-6 ==> Sun-Sat */
-{
-    static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4};
-    y -= m < 3;
-    return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7;
-}
-
-/*
- * Note: the TOD should store the current GMT
- */
-
-int m48_tod_set(int year,		/* 1980-2079 */
-		int month,		/* 01-12 */
-		int day,		/* 01-31 */
-		int hour,		/* 00-23 */
-		int minute,		/* 00-59 */
-		int second)		/* 00-59 */
-
-{
-    SYS_TOD_UNPROTECT();
-
-    M48_ADDR[CONTROL] |= 0x80;	/* Set WRITE bit */
-
-    M48_ADDR[YEAR] = to_bcd(year % 100);
-    M48_ADDR[MONTH] = to_bcd(month);
-    M48_ADDR[DAY] = to_bcd(day);
-    M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1;
-    M48_ADDR[HOUR] = to_bcd(hour);
-    M48_ADDR[MINUTE] = to_bcd(minute);
-    M48_ADDR[SECOND] = to_bcd(second);
-
-    M48_ADDR[CONTROL] &= ~0x80;	/* Clear WRITE bit */
-
-    SYS_TOD_PROTECT();
-
-    return 0;
-}
-
-/*
- * Note: the TOD should store the current GMT
- */
-
-int m48_tod_get(int *year,		/* 1980-2079 */
-		int *month,		/* 01-12 */
-		int *day,		/* 01-31 */
-		int *hour,		/* 00-23 */
-		int *minute,		/* 00-59 */
-		int *second)		/* 00-59 */
-{
-    int y;
-
-    SYS_TOD_UNPROTECT();
-
-    M48_ADDR[CONTROL] |= 0x40;	/* Set READ bit */
-
-    y = from_bcd(M48_ADDR[YEAR]);
-    *year = y < 80 ? 2000 + y : 1900 + y;
-    *month = from_bcd(M48_ADDR[MONTH]);
-    *day = from_bcd(M48_ADDR[DAY]);
-    /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */
-    *hour = from_bcd(M48_ADDR[HOUR]);
-    *minute = from_bcd(M48_ADDR[MINUTE]);
-    *second = from_bcd(M48_ADDR[SECOND] & 0x7f);
-
-    M48_ADDR[CONTROL] &= ~0x40;	/* Clear READ bit */
-
-    SYS_TOD_PROTECT();
-
-    return 0;
-}
-
-int m48_tod_get_second(void)
-{
-    return from_bcd(M48_ADDR[SECOND] & 0x7f);
-}
-
-/*
- * Watchdog function
- *
- *  If usec is 0, the watchdog timer is disarmed.
- *
- *  If usec is non-zero, the watchdog timer is armed (or re-armed) for
- *    approximately usec microseconds (if the exact requested usec is
- *    not supported by the chip, the next higher available value is used).
- *
- *  Minimum watchdog timeout = 62500 usec
- *  Maximum watchdog timeout = 124 sec (124000000 usec)
- */
-
-void m48_watchdog_arm(int usec)
-{
-    int		mpy, res;
-
-    SYS_TOD_UNPROTECT();
-
-    if (usec == 0) {
-	res = 0;
-	mpy = 0;
-    } else if (usec < 2000000) {	/* Resolution: 1/16s if below 2s */
-	res = 0;
-	mpy = (usec + 62499) / 62500;
-    } else if (usec < 8000000) {	/* Resolution: 1/4s if below 8s */
-	res = 1;
-	mpy = (usec + 249999) / 250000;
-    } else if (usec < 32000000) {	/* Resolution: 1s if below 32s */
-	res = 2;
-	mpy = (usec + 999999) / 1000000;
-    } else {				/* Resolution: 4s up to 124s */
-	res = 3;
-	mpy = (usec + 3999999) / 4000000;
-	if (mpy > 31)
-	    mpy = 31;
-    }
-
-    M48_ADDR[WATCH] = (0x80 |		/* Steer to RST signal (IRQ = N/C) */
-		       mpy << 2 |
-		       res);
-
-    SYS_TOD_PROTECT();
-}
-
-/*
- * U-Boot RTC support.
- */
-int
-rtc_get( struct rtc_time *tmp )
-{
-	m48_tod_get(&tmp->tm_year,
-		    &tmp->tm_mon,
-		    &tmp->tm_mday,
-		    &tmp->tm_hour,
-		    &tmp->tm_min,
-		    &tmp->tm_sec);
-	tmp->tm_yday = 0;
-	tmp->tm_isdst= 0;
-
-#ifdef RTC_DEBUG
-	printf( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
-#endif
-
-	return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
-	m48_tod_set(tmp->tm_year,		/* 1980-2079 */
-		    tmp->tm_mon,		/* 01-12 */
-		    tmp->tm_mday,              /* 01-31 */
-		    tmp->tm_hour,		/* 00-23 */
-		    tmp->tm_min,		/* 00-59 */
-		    tmp->tm_sec);		/* 00-59 */
-
-#ifdef RTC_DEBUG
-	printf( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
-		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
-		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-
-	return 0;
-}
-
-void
-rtc_reset (void)
-{
-  m48_tod_init();
-}
diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c
deleted file mode 100644
index be455bb..0000000
--- a/board/bmw/ns16550.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/powerpc/boot/ns16550.c)
- * modified to use CONFIG_SYS_ISA_MEM and new defines
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-typedef struct NS16550 *NS16550_t;
-
-const NS16550_t COM_PORTS[] =
-	{ (NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4500),
-(NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4600) };
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
-	volatile struct NS16550 *com_port;
-
-	com_port = (struct NS16550 *) COM_PORTS[chan];
-	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE;	/* Access baud rate */
-	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
-	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
-	com_port->mcr = MCR_RTS;	/* RTS/DTR */
-	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
-	return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
-	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE;	/* Access baud rate */
-	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
-	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
-	com_port->mcr = MCR_RTS;	/* RTS/DTR */
-	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
-	while ((com_port->lsr & LSR_THRE) == 0);
-	com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
-	while ((com_port->lsr & LSR_DR) == 0);
-	return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
-	return ((com_port->lsr & LSR_DR) != 0);
-}
diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h
deleted file mode 100644
index 2087a4a..0000000
--- a/board/bmw/ns16550.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/powerpc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CONFIG_SYS_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- * further modified to support the 8245 duart
- * modifications (c) Paul Jimenez, Musenki, Inc. 2001.
- */
-
-
-struct NS16550 {
-	unsigned char rbrthrdlb;	/* 0 */
-	unsigned char ierdmb;		/* 1 */
-	unsigned char iirfcrafr;	/* 2 */
-	unsigned char lcr;		/* 3 */
-	unsigned char mcr;		/* 4 */
-	unsigned char lsr;		/* 5 */
-	unsigned char msr;		/* 6 */
-	unsigned char scr;		/* 7 */
-	unsigned char reserved[2];	/* 8 & 9 */
-	unsigned char dsr;		/* 10 */
-	unsigned char dcr;		/* 11 */
-};
-
-
-#define rbr rbrthrdlb
-#define thr rbrthrdlb
-#define dll rbrthrdlb
-#define ier ierdmb
-#define dlm ierdmb
-#define iir iirfcrafr
-#define fcr iirfcrafr
-#define afr iirfcrafr
-
-#define FCR_FIFO_EN     0x01	/*fifo enable */
-#define FCR_RXSR        0x02	/*receiver soft reset */
-#define FCR_TXSR        0x04	/*transmitter soft reset */
-#define FCR_DMS		0x08	/* DMA Mode Select */
-
-#define MCR_RTS         0x02	/* Readyu to Send */
-#define MCR_LOOP	0x10	/* Local loopback mode enable */
-/* #define MCR_DTR         0x01    noton 8245 duart */
-/* #define MCR_DMA_EN      0x04    noton 8245 duart */
-/* #define MCR_TX_DFR      0x08    noton 8245 duart */
-
-#define LCR_WLS_MSK 0x03	/* character length slect mask */
-#define LCR_WLS_5   0x00	/* 5 bit character length */
-#define LCR_WLS_6   0x01	/* 6 bit character length */
-#define LCR_WLS_7   0x02	/* 7 bit character length */
-#define LCR_WLS_8   0x03	/* 8 bit character length */
-#define LCR_STB     0x04	/* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN     0x08	/* Parity eneble */
-#define LCR_EPS     0x10	/* Even Parity Select */
-#define LCR_STKP    0x20	/* Stick Parity */
-#define LCR_SBRK    0x40	/* Set Break */
-#define LCR_BKSE    0x80	/* Bank select enable - aka DLAB on 8245 */
-
-#define LSR_DR      0x01	/* Data ready */
-#define LSR_OE      0x02	/* Overrun */
-#define LSR_PE      0x04	/* Parity error */
-#define LSR_FE      0x08	/* Framing error */
-#define LSR_BI      0x10	/* Break */
-#define LSR_THRE    0x20	/* Xmit holding register empty */
-#define LSR_TEMT    0x40	/* Xmitter empty */
-#define LSR_ERR     0x80	/* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1     0x03
-
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc (volatile struct NS16550 *com_port);
-int NS16550_tstc (volatile struct NS16550 *com_port);
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);
diff --git a/board/bmw/serial.c b/board/bmw/serial.c
deleted file mode 100644
index 08f449c..0000000
--- a/board/bmw/serial.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "ns16550.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_CONS_INDEX == 1
-static struct NS16550 *console =
-		(struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
-#elif CONFIG_CONS_INDEX == 2
-static struct NS16550 *console =
-		(struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
-#else
-#error no valid console defined
-#endif
-
-extern ulong get_bus_freq (ulong);
-
-static int bmw_serial_init(void)
-{
-	int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
-
-	NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
-
-	return (0);
-}
-
-static void bmw_serial_putc(const char c)
-{
-	if (c == '\n') {
-		serial_putc ('\r');
-	}
-	NS16550_putc (console, c);
-}
-
-static void bmw_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-
-static int bmw_serial_getc(void)
-{
-	return NS16550_getc (console);
-}
-
-static int bmw_serial_tstc(void)
-{
-	return NS16550_tstc (console);
-}
-
-static void bmw_serial_setbrg(void)
-{
-	int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
-
-	NS16550_reinit (console, clock_divisor);
-}
-
-static struct serial_device bmw_serial_drv = {
-	.name	= "bmw_serial",
-	.start	= bmw_serial_init,
-	.stop	= NULL,
-	.setbrg	= bmw_serial_setbrg,
-	.putc	= bmw_serial_putc,
-	.puts	= bmw_serial_puts,
-	.getc	= bmw_serial_getc,
-	.tstc	= bmw_serial_tstc,
-};
-
-void bmw_serial_initialize(void)
-{
-	serial_register(&bmw_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &bmw_serial_drv;
-}
diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c
deleted file mode 100644
index 348dfa0..0000000
--- a/board/c2mon/c2mon.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-const uint sdram_table[] =
-{
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
-	0x1FF77C47, /* last */
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
-	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
-	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
-					    _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Refresh  (Offset 30 in UPMA RAM)
-	 */
-	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC84, 0xFFFFFC07, /* last */
-				_NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Exception. (Offset 3c in UPMA RAM)
-	 */
-	0x7FFFFC07, /* last */
-		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	char buf[64];
-	int i;
-	int l = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: TTTech C2MON ");
-
-	for (i = 0; i < l;  ++i) {
-		if (buf[i] == ' ')
-			break;
-		putc (buf[i]);
-	}
-
-	putc ('\n');
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long reg;
-	long int size8, size9;
-	long int size = 0;
-
-	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
-
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller bank 2 the SDRAM bank 2 at physical address 0.
-	 */
-	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
-
-	/* perform SDRAM initializsation sequence */
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
-	udelay (1);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (1000);
-
-	/*
-	 * Check Bank 0 Memory Size
-	 *
-	 * try 8 column mode
-	 */
-	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
-			   SDRAM_BASE2_PRELIM,
-			   SDRAM_MAX_SIZE);
-
-	udelay (1000);
-
-	/*
-	 * try 9 column mode
-	 */
-	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
-			   SDRAM_BASE2_PRELIM,
-			   SDRAM_MAX_SIZE);
-
-	if (size8 < size9) {		/* leave configuration at 9 columns */
-		size = size9;
-/*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
-	} else {			/* back to 8 columns            */
-		size = size8;
-		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
-		udelay (500);
-/*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
-	}
-
-	udelay (1000);
-
-	/*
-	 * Adjust refresh rate depending on SDRAM type
-	 * For types > 128 MBit leave it at the current (fast) rate
-	 */
-	if (size < 0x02000000) {
-		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
-		udelay (1000);
-	}
-
-	/*
-	 * Final mapping
-	 */
-	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-	/*
-	 * No bank 1
-	 *
-	 * invalidate bank
-	 */
-	memctl->memc_br3 = 0;
-
-	/* adjust refresh rate depending on SDRAM type, one bank */
-	reg = memctl->memc_mptpr;
-	reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-	memctl->memc_mptpr = reg;
-
-	udelay (10000);
-
-	return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-						   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size(base, maxsize));
-}
diff --git a/board/c2mon/flash.c b/board/c2mon/flash.c
deleted file mode 100644
index d33cb6c..0000000
--- a/board/c2mon/flash.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0, size_b1;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
-	if (size_b1 > size_b0) {
-		printf ("## ERROR: "
-			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-			size_b1, size_b1<<20,
-			size_b0, size_b0<<20
-		);
-		flash_info[0].flash_id	= FLASH_UNKNOWN;
-		flash_info[1].flash_id	= FLASH_UNKNOWN;
-		flash_info[0].sector_count	= -1;
-		flash_info[1].sector_count	= -1;
-		flash_info[0].size		= 0;
-		flash_info[1].size		= 0;
-		return (0);
-	}
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-		      &flash_info[0]);
-#endif
-
-	if (size_b1) {
-		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
-				    BR_MS_GPCM | BR_V;
-
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
-					  &flash_info[1]);
-
-		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_SYS_MONITOR_BASE,
-			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[1]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-			      &flash_info[1]);
-#endif
-	} else {
-		memctl->memc_br1 = 0;		/* invalidate bank */
-
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-	}
-
-	flash_info[0].size = size_b0;
-	flash_info[1].size = size_b1;
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	switch (value) {
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c
deleted file mode 100644
index 2267829..0000000
--- a/board/c2mon/pcmcia.c
+++ /dev/null
@@ -1,282 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef	CONFIG_PCMCIA
-
-#if	defined(CONFIG_CMD_PCMCIA)
-#define	CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define	CONFIG_PCMCIA
-#endif
-
-#ifdef	CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "C2MON"
-
-static void cfg_ports (void)
-{
-	volatile immap_t	*immap;
-	volatile cpm8xx_t	*cp;
-	ushort sreg;
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
-	/*
-	* Configure Port C for TPS2211 PC-Card Power-Interface Switch
-	*
-	* Switch off all voltages, assert shutdown
-	*/
-	sreg = immap->im_ioport.iop_pcdat;
-	sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1);	/* VAVPP => Hi-Z */
-	sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1);	/* 3V and 5V off */
-	immap->im_ioport.iop_pcdat = sreg;
-
-	immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS);
-	immap->im_ioport.iop_pcdir |=   TPS2211_OUTPUTS;
-
-	debug ("Set Port C: PAR:     %04x DIR:     %04x DAT:     %04x\n",
-	       immap->im_ioport.iop_pcpar,
-	       immap->im_ioport.iop_pcdir,
-	       immap->im_ioport.iop_pcdat);
-
-	/*
-	* Configure Port B for TPS2211 PC-Card Power-Interface Switch
-	*
-	* Over-Current Input only
-	*/
-	cp->cp_pbpar &= ~(TPS2211_INPUTS);
-	cp->cp_pbdir &= ~(TPS2211_INPUTS);
-
-	debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
-	       cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
-	volatile immap_t	*immap;
-	volatile cpm8xx_t	*cp;
-	volatile pcmconf8xx_t	*pcmp;
-	volatile sysconf8xx_t	*sysp;
-	uint reg, pipr, mask;
-	ushort sreg;
-	int i;
-
-	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
-	udelay(10000);
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
-	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
-	cfg_ports ();
-
-	/*
-	* Configure SIUMCR to enable PCMCIA port B
-	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
-	*/
-	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
-
-	/* clear interrupt state, and disable interrupts */
-	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
-	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
-	/*
-	* Disable interrupts, DMA, and PCMCIA buffers
-	* (isolate the interface) and assert RESET signal
-	*/
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = 0;
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	/*
-	* Make sure there is a card in the slot, then configure the interface.
-	*/
-	udelay(10000);
-	debug ("[%d] %s: PIPR(%p)=0x%x\n",
-	       __LINE__,__FUNCTION__,
-	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
-		printf ("   No Card found\n");
-		return (1);
-	}
-
-	/*
-	* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
-	*/
-	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
-	pipr = pcmp->pcmc_pipr;
-	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
-	       pipr,
-	       (reg&PCMCIA_VS1(slot))?"n":"ff",
-	       (reg&PCMCIA_VS2(slot))?"n":"ff");
-
-	sreg = immap->im_ioport.iop_pcdat;
-	if ((pipr & mask) == mask) {
-		sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1 |	/* VAVPP => Hi-Z */
-				TPS2211_VCCD1);			/* 5V on	*/
-		sreg &= ~(TPS2211_VCCD0);			/* 3V off	*/
-		puts (" 5.0V card found: ");
-	} else {
-		sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1 |	/* VAVPP => Hi-Z */
-				TPS2211_VCCD0);			/* 3V on	*/
-		sreg &= ~(TPS2211_VCCD1);			/* 5V off	*/
-		puts (" 3.3V card found: ");
-	}
-
-	debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n",
-	       sreg,
-	       ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off",
-	       (!(sreg & TPS2211_VCCD0) &&  (sreg & TPS2211_VCCD1)) ? "on" : "off"
-	      );
-
-	immap->im_ioport.iop_pcdat = sreg;
-
-	/*  Wait 500 ms; use this to check for over-current */
-	for (i=0; i<5000; ++i) {
-		if ((cp->cp_pbdat & TPS2211_OC) == 0) {
-			printf ("   *** Overcurrent - Safety shutdown ***\n");
-			immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1);
-			return (1);
-		}
-		udelay (100);
-	}
-
-	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
-	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-
-	udelay(250000);	/* some cards need >150 ms to come up :-( */
-
-	debug ("# hardware_enable done\n");
-
-	return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
-	volatile immap_t	*immap;
-	volatile cpm8xx_t	*cp;
-	volatile pcmconf8xx_t	*pcmp;
-	u_long reg;
-
-	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
-	/* Configure PCMCIA General Control Register */
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = 0;
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-
-	/* ALl voltages off / Hi-Z */
-	immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 |
-			TPS2211_VCCD0 | TPS2211_VCCD1 );
-
-	udelay(10000);
-
-	return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
-	volatile immap_t	*immap;
-	volatile pcmconf8xx_t	*pcmp;
-	u_long reg;
-	ushort sreg;
-
-	debug ("voltage_set: "
-			PCMCIA_BOARD_MSG
-			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
-	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-	/*
-	 * Disable PCMCIA buffers (isolate the interface)
-	 * and assert RESET signal
-	 */
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = PCMCIA_PGCRX(_slot_);
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	/*
-	* Configure Port C pins for
-	* 5 Volts Enable and 3 Volts enable,
-	* Turn all power pins to Hi-Z
-	*/
-	debug ("PCMCIA power OFF\n");
-	cfg_ports ();	/* Enables switch, but all in Hi-Z */
-
-	sreg  = immap->im_ioport.iop_pcdat;
-	sreg |= TPS2211_VPPD0 | TPS2211_VPPD1;		/* VAVPP always Hi-Z */
-
-	switch(vcc) {
-		case  0:			break;	/* Switch off		*/
-		case 33: sreg |=  TPS2211_VCCD0;	/* Switch on 3.3V	*/
-		sreg &= ~TPS2211_VCCD1;
-		break;
-		case 50: sreg &= ~TPS2211_VCCD0;	/* Switch on 5.0V	*/
-		sreg |=  TPS2211_VCCD1;
-		break;
-		default:			goto done;
-	}
-
-	/* Checking supported voltages */
-
-	debug ("PIPR: 0x%x --> %s\n",
-	       pcmp->pcmc_pipr,
-	       (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
-	immap->im_ioport.iop_pcdat = sreg;
-
-#ifdef DEBUG
-{
-	char *s;
-
-	if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) {
-		s = "at 3.3V";
-	} else if (!(sreg & TPS2211_VCCD0) &&  (sreg & TPS2211_VCCD1)) {
-		s = "at 5.0V";
-	} else {
-		s = "down";
-	}
-	printf ("PCMCIA powered %s\n", s);
-}
-#endif
-
-done:
-	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
-	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
-	       slot+'A');
-	return (0);
-}
-
-#endif	/* CONFIG_PCMCIA */
diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug
deleted file mode 100644
index c771102..0000000
--- a/board/c2mon/u-boot.lds.debug
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds
index c4039ed..d054f20 100644
--- a/board/cobra5272/u-boot.lds
+++ b/board/cobra5272/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/cogent/serial.c b/board/cogent/serial.c
index cd4a976..20631d1 100644
--- a/board/cogent/serial.c
+++ b/board/cogent/serial.c
@@ -68,12 +68,6 @@ static void cogent_serial_putc(const char c)
 	cma_mb_reg_write (&mbsp->ser_thr, c);
 }
 
-static void cogent_serial_puts(const char *s)
-{
-	while (*s != '\0')
-		serial_putc (*s++);
-}
-
 static int cogent_serial_getc(void)
 {
 	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
@@ -96,7 +90,7 @@ static struct serial_device cogent_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= cogent_serial_setbrg,
 	.putc	= cogent_serial_putc,
-	.puts	= cogent_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= cogent_serial_getc,
 	.tstc	= cogent_serial_tstc,
 };
diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds
index 2393d8d..2a6027f 100644
--- a/board/cogent/u-boot.lds
+++ b/board/cogent/u-boot.lds
@@ -70,9 +70,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug
index 99c48f2..dc8c4e9 100644
--- a/board/cogent/u-boot.lds.debug
+++ b/board/cogent/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile
index 7f7287e..fa5c510 100644
--- a/board/compal/paz00/Makefile
+++ b/board/compal/paz00/Makefile
@@ -20,9 +20,11 @@ $(shell mkdir -p $(obj)../../nvidia/common)
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= $(BOARD).o
-COBJS	+= ../../nvidia/common/board.o
+COBJS-y	:= $(BOARD).o
 
+include ../../nvidia/common/common.mk
+
+COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile
index ff07879..cc844d2 100644
--- a/board/compulab/trimslice/Makefile
+++ b/board/compulab/trimslice/Makefile
@@ -28,9 +28,11 @@ $(shell mkdir -p $(obj)../../nvidia/common)
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= $(BOARD).o
-COBJS	+= ../../nvidia/common/board.o
+COBJS-y	:= $(BOARD).o
 
+include ../../nvidia/common/common.mk
+
+COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile
index 5c6b78f..ac1d174 100644
--- a/board/cpc45/Makefile
+++ b/board/cpc45/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	= $(BOARD).o flash.o plx9030.o pd67290.o
+COBJS	= $(BOARD).o flash.o plx9030.o pd67290.o ide.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c
index 1178822..2200806 100644
--- a/board/cpc45/cpc45.c
+++ b/board/cpc45/cpc45.c
@@ -260,21 +260,6 @@ int pcmcia_init(void)
 
 #endif
 
-# ifdef CONFIG_IDE_LED
-void ide_led (uchar led, uchar status)
-{
-	u_char  val;
-	/* We have one PCMCIA slot and use LED H4 for the IDE Interface */
-	val = readb(BCSR_BASE + 0x04);
-	if (status) {				/* led on */
-		val |= B_CTRL_LED0;
-	} else {
-		val &= ~B_CTRL_LED0;
-	}
-	writeb(val, BCSR_BASE + 0x04);
-}
-# endif
-
 int board_eth_init(bd_t *bis)
 {
 	return pci_eth_init(bis);
diff --git a/board/cpc45/ide.c b/board/cpc45/ide.c
new file mode 100644
index 0000000..03be59f
--- /dev/null
+++ b/board/cpc45/ide.c
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <ata.h>
+#include <asm/io.h>
+
+#define EIEIO		__asm__ volatile ("eieio")
+#define SYNC		__asm__ volatile ("sync")
+
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	uchar i;
+	volatile uchar *pbuf_even =
+		(uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+	volatile uchar *pbuf_odd =
+		(uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+	ushort *dbuf = (ushort *) sect_buf;
+
+	while (words--) {
+		for (i = 0; i < 2; i++) {
+			*(((uchar *) (dbuf)) + 1) = *pbuf_even;
+			*(uchar *) dbuf = *pbuf_odd;
+			dbuf += 1;
+		}
+	}
+}
+
+void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+	uchar *dbuf;
+	volatile uchar *pbuf_even;
+	volatile uchar *pbuf_odd;
+
+	pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+	pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+	dbuf = (uchar *) sect_buf;
+	while (words--) {
+		*dbuf++ = *pbuf_even;
+		EIEIO;
+		SYNC;
+		*dbuf++ = *pbuf_odd;
+		EIEIO;
+		SYNC;
+		*dbuf++ = *pbuf_even;
+		EIEIO;
+		SYNC;
+		*dbuf++ = *pbuf_odd;
+		EIEIO;
+		SYNC;
+	}
+}
+
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	uchar *dbuf;
+	volatile uchar *pbuf_even;
+	volatile uchar *pbuf_odd;
+
+	pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+	pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+	dbuf = (uchar *) sect_buf;
+	while (shorts--) {
+		EIEIO;
+		*dbuf++ = *pbuf_even;
+		EIEIO;
+		*dbuf++ = *pbuf_odd;
+	}
+}
+
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+	uchar *dbuf;
+	volatile uchar *pbuf_even;
+	volatile uchar *pbuf_odd;
+
+	pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+	pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+	dbuf = (uchar *) sect_buf;
+	while (words--) {
+		EIEIO;
+		*pbuf_even = *dbuf++;
+		EIEIO;
+		*pbuf_odd = *dbuf++;
+		EIEIO;
+		*pbuf_even = *dbuf++;
+		EIEIO;
+		*pbuf_odd = *dbuf++;
+	}
+}
+
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+	uchar *dbuf;
+	volatile uchar *pbuf_even;
+	volatile uchar *pbuf_odd;
+
+	pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+	pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+	dbuf = (uchar *) sect_buf;
+	while (shorts--) {
+		EIEIO;
+		*pbuf_even = *dbuf++;
+		EIEIO;
+		*pbuf_odd = *dbuf++;
+	}
+}
+
+void ide_led(uchar led, uchar status)
+{
+	u_char	val;
+	/* We have one PCMCIA slot and use LED H4 for the IDE Interface */
+	val = readb(BCSR_BASE + 0x04);
+	if (status)				/* led on */
+		val |= B_CTRL_LED0;
+	else
+		val &= ~B_CTRL_LED0;
+
+	writeb(val, BCSR_BASE + 0x04);
+}
+
diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug
index fcf8ebb..d7a2e56 100644
--- a/board/cray/L1/u-boot.lds.debug
+++ b/board/cray/L1/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
index 3b10114..8a306d6 100644
--- a/board/dave/PPChameleonEVB/u-boot.lds
+++ b/board/dave/PPChameleonEVB/u-boot.lds
@@ -74,9 +74,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index 6f6e065..c5fd93c 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -47,6 +47,12 @@ SECTIONS
 
 	. = ALIGN(4);
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
+	} >.sram
+
 	. = ALIGN(4);
 	.rel.dyn : {
 		__rel_dyn_start = .;
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index b3a41af..86dc172 100644
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -58,6 +58,11 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
+
+	. = ALIGN(4);
 	__rel_dyn_start = .;
 	__rel_dyn_end = .;
 	__dynsym_start = .;
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
index 4a59cea..8a871cf 100644
--- a/board/dbau1x00/u-boot.lds
+++ b/board/dbau1x00/u-boot.lds
@@ -54,10 +54,9 @@ SECTIONS
 
 	.sdata  : { *(.sdata*) }
 
-	.u_boot_cmd : {
-	  __u_boot_cmd_start = .;
-	  *(.u_boot_cmd)
-	  __u_boot_cmd_end = .;
+	. = ALIGN(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
 
 	uboot_end_data = .;
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
index 01ec390..1bd1700 100644
--- a/board/dvlhost/u-boot.lds
+++ b/board/dvlhost/u-boot.lds
@@ -54,11 +54,11 @@ SECTIONS
 		*(.got)
 	}
 	. =.;
-	__u_boot_cmd_start =.;
-	.u_boot_cmd : {
-		*(.u_boot_cmd)
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
 	}
-	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
 	.rel.dyn : {
diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds
index fd4e8a5..c8d3894 100644
--- a/board/eltec/mhpc/u-boot.lds
+++ b/board/eltec/mhpc/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug
index c771102..92796e6 100644
--- a/board/eltec/mhpc/u-boot.lds.debug
+++ b/board/eltec/mhpc/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds
index fb06648..22626d3 100644
--- a/board/emk/top860/u-boot.lds
+++ b/board/emk/top860/u-boot.lds
@@ -67,9 +67,11 @@ SECTIONS
 
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds
index 332b35a..1dcc22a 100644
--- a/board/ep88x/u-boot.lds
+++ b/board/ep88x/u-boot.lds
@@ -62,9 +62,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index aa001df..4ef10e7 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -30,7 +30,6 @@
 #include <ide.h>
 #include <pci.h>
 
-extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
 int cpci_hd_type;
 
 int ata_device(int dev)
diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c
index 25f8950..160e0e0 100644
--- a/board/esd/cpci750/serial.c
+++ b/board/esd/cpci750/serial.c
@@ -75,21 +75,13 @@ static void cpci750_serial_setbrg(void)
 	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
 }
 
-
-static void cpci750_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
 static struct serial_device cpci750_serial_drv = {
 	.name	= "cpci750_serial",
 	.start	= cpci750_serial_init,
 	.stop	= NULL,
 	.setbrg	= cpci750_serial_setbrg,
 	.putc	= cpci750_serial_putc,
-	.puts	= cpci750_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= cpci750_serial_getc,
 	.tstc	= cpci750_serial_tstc,
 };
diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds
index b15948d..7eca183 100644
--- a/board/esd/dasa_sim/u-boot.lds
+++ b/board/esd/dasa_sim/u-boot.lds
@@ -73,9 +73,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds
index 71f0fd2..ca7df45 100644
--- a/board/esd/pmc440/u-boot-nand.lds
+++ b/board/esd/pmc440/u-boot-nand.lds
@@ -102,10 +102,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+		#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds
index f697ccd..0d6a0f3 100644
--- a/board/esd/tasreg/u-boot.lds
+++ b/board/esd/tasreg/u-boot.lds
@@ -65,9 +65,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds
index 163b83d..fe5cf09 100644
--- a/board/esteem192e/u-boot.lds
+++ b/board/esteem192e/u-boot.lds
@@ -36,7 +36,6 @@ SECTIONS
     arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
     net/libnet.o			(.text*)
     board/esteem192e/libesteem192e.o	(.text*)
-    *(.text.*printf)
 
     . = env_offset;
     common/env_embedded.o		(.text*)
@@ -75,9 +74,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c
deleted file mode 100644
index abefe4a..0000000
--- a/board/etx094/etx094.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static void read_hw_vers (void);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_	0xFFFFFFFF
-
-const uint sdram_table[] = {
-
-	/* single read   (offset 0x00 in upm ram) */
-
-	0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04,
-	0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_,
-
-	/* burst read    (offset 0x08 in upm ram) */
-
-	0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04,
-	0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00,
-	0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-	/* single write  (offset 0x18 in upm ram) */
-
-	0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00,
-	0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_,
-
-	/* burst write   (offset 0x20 in upm ram) */
-
-	0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00,
-	0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05,
-
-	/* init part1      (offset 0x28 in upm ram) */
-
-	0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34,
-	0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-	/* refresh   (offset 0x30 in upm ram) */
-
-	0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05,
-
-	/* init part2     (offset 0x34 in upm ram) */
-
-	0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34,
-	0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_,
-
-	/* exception     (offset 0x3C in upm ram) */
-
-	0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ETX ID string (ETX_xxx...)
- *
- * Return 1 always.
- */
-
-int checkboard (void)
-{
-	char buf[64];
-	int i;
-	int l = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: ");
-
-#ifdef SB_ETX094
-	gd->board_type = 0; /* 0 = 2SDRAM-Device */
-#else
-	gd->board_type = 1; /* 1 = 1SDRAM-Device */
-#endif
-
-	if (l < 0 || strncmp(buf, "ETX_", 4)) {
-		puts ("### No HW ID - assuming ETX_094\n");
-		read_hw_vers ();
-		return (0);
-	}
-
-	for (i = 0; i < l; ++i) {
-		if (buf[i] == ' ')
-			break;
-		putc(buf[i]);
-	}
-	putc ('\n');
-
-	read_hw_vers ();
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size_b0, size_b1, size8, size9;
-
-	upmconfig (UPMA, (uint *) sdram_table,
-			   sizeof (sdram_table) / sizeof (uint));
-
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;	/* MPTPR_PTP_DIV32 0x0200 */
-
-	/* A3(SDRAM)=0      => Bursttype = Sequential
-	 * A2-A0(SDRAM)=010 => Burst length = 4
-	 * A4-A6(SDRAM)=010 => CasLat=2
-	 */
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
-	 * preliminary addresses - these have to be modified after the
-	 * SDRAM size has been determined.
-	 */
-	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
-	if (board_type == 0) {	/* "L" type boards have only one bank SDRAM */
-		memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
-		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-	}
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
-
-	/* perform SDRAM initializsation sequence */
-
-	memctl->memc_mcr = 0x80004128;	/* SDRAM bank 0 (CS2) - Init Part 1 */
-	memctl->memc_mcr = 0x80004734;	/* SDRAM bank 0 (CS2) - Init Part 2 */
-	udelay (1);
-
-	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
-		memctl->memc_mcr = 0x80006128;	/* SDRAM bank 1 (CS3) - Init Part 1 */
-		memctl->memc_mcr = 0x80006734;	/* SDRAM bank 1 (CS3) - Init Part 2 */
-		udelay (1);
-	}
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (1000);
-
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 *
-	 * try 8 column mode
-	 */
-	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
-					   SDRAM_MAX_SIZE);
-
-	udelay (1000);
-
-	/*
-	 * try 9 column mode
-	 */
-	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
-					   SDRAM_MAX_SIZE);
-
-	if (size8 < size9) {		/* leave configuration at 9 columns */
-		size_b0 = size9;
-/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
-	} else {					/* back to 8 columns            */
-		size_b0 = size8;
-		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
-		udelay (500);
-/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
-	}
-
-	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
-		/*
-		 * Check Bank 1 Memory Size
-		 * use current column settings
-		 * [9 column SDRAM may also be used in 8 column mode,
-		 *  but then only half the real size will be used.]
-		 */
-		size_b1 =
-				dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM,
-						   SDRAM_MAX_SIZE);
-/*	debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);	*/
-	} else {
-		size_b1 = 0;
-	}
-
-	udelay (1000);
-
-	/*
-	 * Adjust refresh rate depending on SDRAM type, both banks
-	 * For types > 128 MBit leave it at the current (fast) rate
-	 */
-	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
-		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;	/*DIV16 */
-		udelay (1000);
-	}
-
-	/*
-	 * Final mapping: map bigger bank first
-	 */
-	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
-
-		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-		memctl->memc_br3 =
-			(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-		if (size_b0 > 0) {
-			/*
-			 * Position Bank 0 immediately above Bank 1
-			 */
-			memctl->memc_or2 =
-				((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-			memctl->memc_br2 =
-				((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-				+ size_b1;
-		} else {
-			unsigned long reg;
-
-			/*
-			 * No bank 0
-			 *
-			 * invalidate bank
-			 */
-			memctl->memc_br2 = 0;
-
-			/* adjust refresh rate depending on SDRAM type, one bank */
-			reg = memctl->memc_mptpr;
-			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-			memctl->memc_mptpr = reg;
-		}
-
-	} else {			/* SDRAM Bank 0 is bigger - map first   */
-
-		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-		memctl->memc_br2 =
-				(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-		if (size_b1 > 0) {
-			/*
-			 * Position Bank 1 immediately above Bank 0
-			 */
-			memctl->memc_or3 =
-					((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-			memctl->memc_br3 =
-					((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-					+ size_b0;
-		} else {
-			unsigned long reg;
-
-			/*
-			 * No bank 1
-			 *
-			 * invalidate bank
-			 */
-			memctl->memc_br3 = 0;
-
-			/* adjust refresh rate depending on SDRAM type, one bank */
-			reg = memctl->memc_mptpr;
-			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-			memctl->memc_mptpr = reg;
-		}
-	}
-
-	udelay (10000);
-
-	return (size_b0 + size_b1);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-						   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* HW-ID Table (Bits: 2^9;2^7;2^5) */
-#define HW_ID_0 0x0000
-#define HW_ID_1 0x0020
-#define HW_ID_2 0x0080
-#define HW_ID_3 0x00a0
-#define HW_ID_4 0x0200
-#define HW_ID_5 0x0220
-#define HW_ID_6 0x0280
-#define HW_ID_7 0x02a0
-
-void read_hw_vers ()
-{
-	unsigned short rd_msk = 0x02A0;
-
-	/* HW-ID pin-definition */
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
-	immr->im_ioport.iop_pddir &= ~(rd_msk);
-	immr->im_ioport.iop_pdpar &= ~(rd_msk);
-
-	/* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */
-
-	/* Check the HW-ID */
-	printf ("HW-Version: ");
-	switch (immr->im_ioport.iop_pddat & rd_msk) {
-	case HW_ID_0:
-		printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n");
-		break;
-	case HW_ID_1:
-		printf ("V0.9 / W50037-Q1-D6-1\n");
-		break;
-	case HW_ID_2:
-		printf ("NOT USED - assuming ID#2\n");
-		break;
-	case HW_ID_3:
-		printf ("NOT USED - assuming ID#3\n");
-		break;
-	case HW_ID_4:
-		printf ("NOT USED - assuming ID#4\n");
-		break;
-	case HW_ID_5:
-		printf ("NOT USED - assuming ID#5\n");
-		break;
-	case HW_ID_6:
-		printf ("NOT USED - assuming ID#6\n");
-		break;
-	case HW_ID_7:
-		printf ("NOT USED - assuming ID#7\n");
-		break;
-	default:
-		printf ("###Error###\n");
-		break;
-	}
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/etx094/flash.c b/board/etx094/flash.c
deleted file mode 100644
index 0958e73..0000000
--- a/board/etx094/flash.c
+++ /dev/null
@@ -1,687 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info);
-static int write_word(flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-#ifdef CONFIG_FLASH_16BIT
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
-		BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
-#else
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
-		BR_MS_GPCM | BR_V;
-#endif
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
-			&flash_info[0]);
-
-	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-	memctl->memc_br1 = 0;		/* invalidate bank 1 */
-
-	flash_info[0].size = size_b0;
-
-	return size_b0;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return;
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00002000);
-
-		return;
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-#ifdef CONFIG_FLASH_16BIT
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-#else
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-#endif
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--)
-			info->start[i] = base + i * 0x00020000;
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf("AMD ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf("FUJITSU ");
-		break;
-	case FLASH_MAN_SST:
-		printf("SST ");
-		break;
-	case FLASH_MAN_STM:
-		printf("STM ");
-		break;
-	default:
-		printf("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:
-		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM400T:
-		printf("AM29LV400T (4 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM800B:
-		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM800T:
-		printf("AM29LV800T (8 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM160B:
-		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM160T:
-		printf("AM29LV160T (16 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM320B:
-		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM320T:
-		printf("AM29LV320T (32 Mbit, top boot sector)\n");
-		break;
-	case FLASH_SST200A:
-		printf("39xF200A (2M = 128K x 16)\n");
-		break;
-	case FLASH_SST400A:
-		printf("39xF400A (4M = 256K x 16)\n");
-		break;
-	case FLASH_SST800A:
-		printf("39xF800A (8M = 512K x 16)\n");
-		break;
-	case FLASH_STM800AB:
-		printf("M29W800AB (8M = 512K x 16)\n");
-		break;
-	default:
-		printf("Unknown Chip Type\n");
-		break;
-	}
-
-	printf("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-#ifdef CONFIG_FLASH_16BIT
-	vu_short *s_addr = (vu_short *)addr;
-	s_addr[0x5555] = 0x00AA;
-	s_addr[0x2AAA] = 0x0055;
-	s_addr[0x5555] = 0x0090;
-	value = s_addr[0];
-	value = value|(value<<16);
-#else
-	addr[0x5555] = 0x00AA00AA;
-	addr[0x2AAA] = 0x00550055;
-	addr[0x5555] = 0x00900090;
-	value = addr[0];
-#endif
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	case STM_MANUFACT:
-		info->flash_id = FLASH_MAN_STM;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return 0;			/* no or unknown flash	*/
-	}
-#ifdef CONFIG_FLASH_16BIT
-	value = s_addr[1];
-	value = value|(value<<16);
-#else
-	value = addr[1];			/* device ID		*/
-#endif
-
-	switch (value) {
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-#ifdef CONFIG_FLASH_16BIT
-		info->sector_count = 19;
-		info->size = 0x00100000;	/* => 1 MB */
-#else
-		info->sector_count = 19;
-		info->size = 0x00200000;	/* => 2 MB	*/
-#endif
-		break;
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-#ifdef CONFIG_FLASH_16BIT
-		info->sector_count = 35;
-		info->size = 0x00200000;	/* => 2 MB	*/
-#else
-		info->sector_count = 35;
-		info->size = 0x00400000;	/* => 4 MB	*/
-#endif
-
-		break;
-	case SST_ID_xF200A:
-		info->flash_id += FLASH_SST200A;
-		info->sector_count = 64;	/* 39xF200A (2M = 128K x 16) */
-		info->size = 0x00080000;
-		break;
-	case SST_ID_xF400A:
-		info->flash_id += FLASH_SST400A;
-		info->sector_count = 128;	/* 39xF400A (4M = 256K x 16) */
-		info->size = 0x00100000;
-		break;
-	case SST_ID_xF800A:
-		info->flash_id += FLASH_SST800A;
-		info->sector_count = 256;	/* 39xF800A (8M = 512K x 16) */
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-	case STM_ID_x800AB:
-		info->flash_id += FLASH_STM800AB;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return 0;			/* => no or unknown flash */
-
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00002000);
-	} else {	/* AMD and Fujitsu types */
-		/* set up sector start address table */
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type */
-#ifdef CONFIG_FLASH_16BIT
-
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++)
-				info->start[i] = base +
-					(i * 0x00010000) - 0x00030000;
-#else
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00008000;
-			info->start[2] = base + 0x0000C000;
-			info->start[3] = base + 0x00010000;
-			for (i = 4; i < info->sector_count; i++)
-				info->start[i] = base +
-					(i * 0x00020000) - 0x00060000;
-#endif
-		} else {
-			/* set sector offsets for top boot block type	*/
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00008000;
-			info->start[i--] = base + info->size - 0x0000C000;
-			info->start[i--] = base + info->size - 0x00010000;
-			for (; i >= 0; i--)
-				info->start[i] = base + i * 0x00020000;
-		}
-
-		/* check for protected sectors */
-		for (i = 0; i < info->sector_count; i++) {
-			/*
-			 * read sector protection at sector address:
-			 * (A7 .. A0) = 0x02
-			 * D0 = 1 if protected
-			 */
-#ifdef CONFIG_FLASH_16BIT
-			s_addr = (volatile unsigned short *)(info->start[i]);
-			info->protect[i] = s_addr[2] & 1;
-#else
-			addr = (volatile unsigned long *)(info->start[i]);
-			info->protect[i] = addr[2] & 1;
-#endif
-		}
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-#ifdef CONFIG_FLASH_16BIT
-		s_addr = (volatile unsigned short *)(info->start[0]);
-		*s_addr = 0x00F0;	/* reset bank */
-#else
-		addr = (volatile unsigned long *)info->start[0];
-		*addr = 0x00F000F0;	/* reset bank */
-#endif
-
-	}
-	return info->size;
-}
-
-int	flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long *)(info->start[0]);
-	int flag, prot, sect;
-	ulong start, now, last;
-#ifdef CONFIG_FLASH_16BIT
-	vu_short *s_addr = (vu_short *)addr;
-#endif
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-/*#ifndef CONFIG_FLASH_16BIT
-	ulong type;
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return;
-	}
-#endif*/
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot) {
-		printf("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf("\n");
-	}
-
-	start = get_timer(0);
-	last  = start;
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-#ifdef CONFIG_FLASH_16BIT
-			vu_short *s_sect_addr = (vu_short *)(info->start[sect]);
-#else
-			vu_long	*sect_addr = (vu_long *)(info->start[sect]);
-#endif
-			/* Disable interrupts which might cause a timeout */
-			flag = disable_interrupts();
-
-#ifdef CONFIG_FLASH_16BIT
-
-			/*printf("\ns_sect_addr=%x",s_sect_addr);*/
-			s_addr[0x5555] = 0x00AA;
-			s_addr[0x2AAA] = 0x0055;
-			s_addr[0x5555] = 0x0080;
-			s_addr[0x5555] = 0x00AA;
-			s_addr[0x2AAA] = 0x0055;
-			s_sect_addr[0] = 0x0030;
-#else
-			addr[0x5555] = 0x00AA00AA;
-			addr[0x2AAA] = 0x00550055;
-			addr[0x5555] = 0x00800080;
-			addr[0x5555] = 0x00AA00AA;
-			addr[0x2AAA] = 0x00550055;
-			sect_addr[0] = 0x00300030;
-#endif
-			/* re-enable interrupts if necessary */
-			if (flag)
-				enable_interrupts();
-
-			/* wait at least 80us - let's wait 1 ms */
-			udelay(1000);
-
-#ifdef CONFIG_FLASH_16BIT
-			while ((s_sect_addr[0] & 0x0080) != 0x0080) {
-#else
-			while ((sect_addr[0] & 0x00800080) != 0x00800080) {
-#endif
-				now = get_timer(start);
-				if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf("Timeout\n");
-					return 1;
-				}
-				/* show every second that we're waiting */
-				if ((now - last) > 1000) {
-					putc('.');
-					last = now;
-				}
-			}
-		}
-	}
-
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-#ifdef CONFIG_FLASH_16BIT
-	s_addr[0] = 0x00F0;	/* reset bank */
-#else
-	addr[0] = 0x00F000F0;	/* reset bank */
-#endif
-
-	printf(" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return 4;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	l = addr - wp;
-
-	if (l != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp)
-			data = (data << 8) | (*(uchar *)cp);
-
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp)
-			data = (data << 8) | (*(uchar *)cp);
-
-		rc = write_word(info, wp, data);
-
-		if (rc != 0)
-			return rc;
-
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i)
-			data = (data << 8) | *src++;
-
-		rc = write_word(info, wp, data);
-		if (rc != 0)
-			return rc;
-
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0)
-		return 0;
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp)
-		data = (data << 8) | (*(uchar *)cp);
-
-	return write_word(info, wp, data);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word(flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long *)(info->start[0]);
-
-#ifdef CONFIG_FLASH_16BIT
-	vu_short high_data;
-	vu_short low_data;
-	vu_short *s_addr = (vu_short *)addr;
-#endif
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data)
-		return 2;
-
-#ifdef CONFIG_FLASH_16BIT
-	/* Write the 16 higher-bits */
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	high_data = ((data>>16) & 0x0000ffff);
-
-	s_addr[0x5555] = 0x00AA;
-	s_addr[0x2AAA] = 0x0055;
-	s_addr[0x5555] = 0x00A0;
-
-	*((vu_short *)dest) = high_data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer(0);
-	while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-			return 1;
-	}
-
-	/* Write the 16 lower-bits */
-#endif
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-#ifdef CONFIG_FLASH_16BIT
-	dest += 0x2;
-	low_data = (data & 0x0000ffff);
-
-	s_addr[0x5555] = 0x00AA;
-	s_addr[0x2AAA] = 0x0055;
-	s_addr[0x5555] = 0x00A0;
-	*((vu_short *)dest) = low_data;
-
-#else
-	addr[0x5555] = 0x00AA00AA;
-	addr[0x2AAA] = 0x00550055;
-	addr[0x5555] = 0x00A000A0;
-	*((vu_long *)dest) = data;
-#endif
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer(0);
-
-#ifdef CONFIG_FLASH_16BIT
-	while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
-#else
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-#endif
-
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-			return 1;
-	}
-	return 0;
-}
diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds
deleted file mode 100644
index 8465937..0000000
--- a/board/etx094/u-boot.lds
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    net/libnet.o			(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    *(.text.vsprintf)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c
index 9fd4298..b9ca1d7 100644
--- a/board/evb64260/serial.c
+++ b/board/evb64260/serial.c
@@ -139,20 +139,13 @@ static void evb64260_serial_setbrg(void)
 
 #endif /* CONFIG_MPSC */
 
-static void evb64260_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
 static struct serial_device evb64260_serial_drv = {
 	.name	= "evb64260_serial",
 	.start	= evb64260_serial_init,
 	.stop	= NULL,
 	.setbrg	= evb64260_serial_setbrg,
 	.putc	= evb64260_serial_putc,
-	.puts	= evb64260_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= evb64260_serial_getc,
 	.tstc	= evb64260_serial_tstc,
 };
diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds
index 2d031ef..eac9c07 100644
--- a/board/evb64260/u-boot.lds
+++ b/board/evb64260/u-boot.lds
@@ -70,9 +70,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds
index 9ea0674..6022dbc 100644
--- a/board/fads/u-boot.lds
+++ b/board/fads/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds
index fd4e8a5..c8d3894 100644
--- a/board/flagadm/u-boot.lds
+++ b/board/flagadm/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug
index c771102..92796e6 100644
--- a/board/flagadm/u-boot.lds.debug
+++ b/board/flagadm/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 54cb098..36f7c4f 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -53,6 +53,7 @@ COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P3041DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P5020DS)		+= ics307_clk.o
+COBJS-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
 
 # deal with common files for P-series corenet based devices
 SUBLIB-$(CONFIG_P2041RDB)	+= p_corenet/libp_corenet.o
diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c
index 276ae3c..3c75028 100644
--- a/board/freescale/common/ngpixis.c
+++ b/board/freescale/common/ngpixis.c
@@ -237,13 +237,17 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-U_BOOT_CMD(
-	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
-	"Reset the board using the FPGA sequencer",
+#ifdef CONFIG_SYS_LONGHELP
+static char pixis_help_text[] =
 	"- hard reset to default bank\n"
 	"pixis_reset altbank - reset to alternate bank\n"
 #ifdef DEBUG
 	"pixis_reset dump - display the PIXIS registers\n"
 #endif
-	"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n"
+	"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n";
+#endif
+
+U_BOOT_CMD(
+	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+	"Reset the board using the FPGA sequencer", pixis_help_text
 	);
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 6cd7e51..c92902a 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -32,22 +32,22 @@ void qixis_write(unsigned int reg, u8 value)
 
 void qixis_reset(void)
 {
-	QIXIS_WRITE(rst_ctl, 0x83);
+	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
 }
 
 void qixis_bank_reset(void)
 {
-	QIXIS_WRITE(rcfg_ctl, 0x20);
-	QIXIS_WRITE(rcfg_ctl, 0x21);
+	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 }
 
-/* Set the boot bank to the power-on default bank0 */
+/* Set the boot bank to the power-on default bank */
 void clear_altbank(void)
 {
 	u8 reg;
 
 	reg = QIXIS_READ(brdcfg[0]);
-	reg = reg & ~QIXIS_LBMAP_MASK;
+	reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
 	QIXIS_WRITE(brdcfg[0], reg);
 }
 
@@ -85,11 +85,11 @@ static void qixis_dump_regs(void)
 	printf("ctl_sys	= %02x\n", QIXIS_READ(ctl_sys));
 	printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
 	printf("present = %02x\n", QIXIS_READ(present));
+	printf("present2 = %02x\n", QIXIS_READ(present2));
 	printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
 	printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
 	printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
 	printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
-	printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2));
 }
 #endif
 
@@ -115,7 +115,8 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		for (i = 0; i < ARRAY_SIZE(period); i++) {
 			if (strcmp(argv[2], period[i]) == 0) {
 				/* disable watchdog */
-				QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08);
+				QIXIS_WRITE(rcfg_ctl,
+					rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
 				QIXIS_WRITE(watch, ((i<<2) - 1));
 				QIXIS_WRITE(rcfg_ctl, rcfg);
 				return 0;
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 7a0268a..b98b180 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -26,7 +26,7 @@ struct qixis {
 	u8 stat_sys;
 	u8 stat_alrm;
 	u8 present;
-	u8 ctl_sys2;
+	u8 present2;    /* Presence Status Register 2,0x0c */
 	u8 rcw_ctl;
 	u8 ctl_led;
 	u8 i2cblk;
@@ -86,12 +86,6 @@ struct qixis {
 	u8 res15[16];
 };
 
-#define QIXIS_BASE		0xffdf0000
-#define QIXIS_LBMAP_SWITCH	7
-#define QIXIS_LBMAP_MASK	0x0f
-#define QIXIS_LBMAP_SHIFT	0
-#define QIXIS_LBMAP_ALTBANK	0x04
-
 u8 qixis_read(unsigned int reg);
 void qixis_write(unsigned int reg, u8 value);
 
diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c
new file mode 100644
index 0000000..7868565
--- /dev/null
+++ b/board/freescale/common/vsc3316_3308.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "vsc3316_3308.h"
+
+#define REVISION_ID_REG		0x7E
+#define INTERFACE_MODE_REG		0x79
+#define CURRENT_PAGE_REGISTER		0x7F
+#define CONNECTION_CONFIG_PAGE		0x00
+#define INPUT_STATE_REG		0x13
+#define GLOBAL_INPUT_ISE1		0x51
+#define GLOBAL_INPUT_ISE2		0x52
+#define GLOBAL_INPUT_LOS		0x55
+#define GLOBAL_CORE_CNTRL		0x5D
+#define OUTPUT_MODE_PAGE		0x23
+#define CORE_CONTROL_PAGE		0x25
+#define CORE_CONFIG_REG		0x75
+
+int vsc_if_enable(unsigned int vsc_addr)
+{
+	u8 data;
+
+	debug("VSC:Configuring VSC at I2C address 0x%2x"
+			" for 2-wire interface\n", vsc_addr);
+
+	/* enable 2-wire Serial InterFace (I2C) */
+	data = 0x02;
+	return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
+}
+
+int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+		unsigned int num_con)
+{
+	unsigned int i;
+	u8 rev_id = 0;
+	int ret;
+
+	debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
+		" for Tx\n", vsc_addr);
+
+	ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+			vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+	/* input state - page 0x13 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Configuring the required input of the switch */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][0], 0x80);
+
+	/* Setting Global Input LOS threshold value */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
+
+	/* config output mode - page 0x23 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn ON the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr,  con_arr[i][1], 0);
+
+	/* configure global core control register, Turn on Global core power */
+	i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+
+	vsc_wp_config(vsc_addr);
+
+	return 0;
+}
+
+int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+		unsigned int num_con)
+{
+	unsigned int i;
+	u8 rev_id = 0;
+	int ret;
+
+	debug("VSC:Initializing VSC3308 at I2C address 0x%x"
+		" for Tx\n", vsc_addr);
+
+	ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+			vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+	/*Configure Global Input ISE and gain */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12);
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12);
+
+	/* input state - page 0x13 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Turning ON the required input of the switch */
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr, con_arr[i][0], 0);
+
+	/* Setting Global Input LOS threshold value */
+	i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
+
+	/* config output mode - page 0x23 */
+	i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn ON the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		i2c_reg_write(vsc_addr,  con_arr[i][1], 0);
+
+	/* configure global core control register, Turn on Global core power */
+	i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+
+	vsc_wp_config(vsc_addr);
+
+	return 0;
+}
+
+void vsc_wp_config(unsigned int vsc_addr)
+{
+	debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr);
+
+	/* For new crosspoint configuration to occur, WP bit of
+	 * CORE_CONFIG_REG should be set 1 and then reset to 0 */
+	i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01);
+	i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0);
+}
diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h
new file mode 100644
index 0000000..effd66d
--- /dev/null
+++ b/board/freescale/common/vsc3316_3308.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __VSC_CROSSBAR_H_
+#define __VSC_CROSSBAR_H	1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+
+int vsc_if_enable(unsigned int vsc_addr);
+int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+		unsigned int num_con);
+int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+		unsigned int num_con);
+void vsc_wp_config(unsigned int vsc_addr);
+
+#endif	/* __VSC_CROSSBAR_H_ */
diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds
index 6e39be1..2c151f2 100644
--- a/board/freescale/m5208evbe/u-boot.lds
+++ b/board/freescale/m5208evbe/u-boot.lds
@@ -69,9 +69,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds
index 3e9f4c3..dbd6f6a 100644
--- a/board/freescale/m52277evb/u-boot.lds
+++ b/board/freescale/m52277evb/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds
index d39e734..00932ae 100644
--- a/board/freescale/m5235evb/u-boot.lds
+++ b/board/freescale/m5235evb/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds
index c4039ed..d054f20 100644
--- a/board/freescale/m5249evb/u-boot.lds
+++ b/board/freescale/m5249evb/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds
index cbd2831..f8116f6 100644
--- a/board/freescale/m5253demo/u-boot.lds
+++ b/board/freescale/m5253demo/u-boot.lds
@@ -69,9 +69,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds
index c4039ed..d054f20 100644
--- a/board/freescale/m5253evbe/u-boot.lds
+++ b/board/freescale/m5253evbe/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds
index 4717036..133ec01 100644
--- a/board/freescale/m5271evb/u-boot.lds
+++ b/board/freescale/m5271evb/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds
index c4039ed..d054f20 100644
--- a/board/freescale/m5272c3/u-boot.lds
+++ b/board/freescale/m5272c3/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds
index 6c2dfe8..fc68de1 100644
--- a/board/freescale/m5275evb/u-boot.lds
+++ b/board/freescale/m5275evb/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds
index 4ba1964..ad49874 100644
--- a/board/freescale/m5282evb/u-boot.lds
+++ b/board/freescale/m5282evb/u-boot.lds
@@ -29,6 +29,9 @@ SECTIONS
   {
     arch/m68k/cpu/mcf52x2/start.o	(.text*)
 
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o      (.text*)
+
     *(.text*)
   }
   _etext = .;
@@ -65,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds
index 80935f2..d25a36f 100644
--- a/board/freescale/m53017evb/u-boot.lds
+++ b/board/freescale/m53017evb/u-boot.lds
@@ -71,9 +71,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds
index 40af8bc..6616594 100644
--- a/board/freescale/m5329evb/u-boot.lds
+++ b/board/freescale/m5329evb/u-boot.lds
@@ -69,9 +69,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds
index 19342ac..bc40fd6 100644
--- a/board/freescale/m5373evb/u-boot.lds
+++ b/board/freescale/m5373evb/u-boot.lds
@@ -69,9 +69,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/siemens/IAD210/Makefile b/board/freescale/m54418twr/Makefile
index bb81507..1e53f48 100644
--- a/board/siemens/IAD210/Makefile
+++ b/board/freescale/m54418twr/Makefile
@@ -1,6 +1,5 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -25,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	= $(BOARD).o flash.o atm.o
+COBJS	= $(BOARD).o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/bmw/config.mk b/board/freescale/m54418twr/config.mk
index a1a44e5..a592335 100644
--- a/board/bmw/config.mk
+++ b/board/freescale/m54418twr/config.mk
@@ -1,6 +1,5 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -21,10 +20,6 @@
 # MA 02111-1307 USA
 #
 
-#
-# BMW board
-#
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
 
-# NOTE: The flags below affect how the BCM570x driver is compiled
-PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\
-		     -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
new file mode 100644
index 0000000..6e57bef
--- /dev/null
+++ b/board/freescale/m54418twr/m54418twr.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	/*
+	 * need to to:
+	 * Check serial flash size. if 2mb evb, else 8mb demo
+	 */
+	puts("Board: ");
+	puts("Freescale MCF54418 Tower System\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize;
+
+#if defined(CONFIG_SERIAL_BOOT)
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	pm_t *pm = (pm_t *) MMAP_PM;
+	u32 i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+
+	out_8(&pm->pmcr0, 0x2E);
+	out_8(&gpio->mscr_sdram, 1);
+
+	clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
+	setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
+
+	out_be32(&sdram->rcrcr, 0x40000000);
+	out_be32(&sdram->padcr, 0x01030203);
+
+	out_be32(&sdram->cr00, 0x01010101);
+	out_be32(&sdram->cr01, 0x00000101);
+	out_be32(&sdram->cr02, 0x01010100);
+	out_be32(&sdram->cr03, 0x01010000);
+	out_be32(&sdram->cr04, 0x00010101);
+	out_be32(&sdram->cr06, 0x00010100);
+	out_be32(&sdram->cr07, 0x00000001);
+	out_be32(&sdram->cr08, 0x01000001);
+	out_be32(&sdram->cr09, 0x00000100);
+	out_be32(&sdram->cr10, 0x00010001);
+	out_be32(&sdram->cr11, 0x00000200);
+	out_be32(&sdram->cr12, 0x01000002);
+	out_be32(&sdram->cr13, 0x00000000);
+	out_be32(&sdram->cr14, 0x00000100);
+	out_be32(&sdram->cr15, 0x02000100);
+	out_be32(&sdram->cr16, 0x02000407);
+	out_be32(&sdram->cr17, 0x02030007);
+	out_be32(&sdram->cr18, 0x02000100);
+	out_be32(&sdram->cr19, 0x0A030203);
+	out_be32(&sdram->cr20, 0x00020708);
+	out_be32(&sdram->cr21, 0x00050008);
+	out_be32(&sdram->cr22, 0x04030002);
+	out_be32(&sdram->cr23, 0x00000004);
+	out_be32(&sdram->cr24, 0x020A0000);
+	out_be32(&sdram->cr25, 0x0C00000E);
+	out_be32(&sdram->cr26, 0x00002004);
+	out_be32(&sdram->cr28, 0x00100010);
+	out_be32(&sdram->cr29, 0x00100010);
+	out_be32(&sdram->cr31, 0x07990000);
+	out_be32(&sdram->cr40, 0x00000000);
+	out_be32(&sdram->cr41, 0x00C80064);
+	out_be32(&sdram->cr42, 0x44520002);
+	out_be32(&sdram->cr43, 0x00C80023);
+	out_be32(&sdram->cr45, 0x0000C350);
+	out_be32(&sdram->cr56, 0x04000000);
+	out_be32(&sdram->cr57, 0x03000304);
+	out_be32(&sdram->cr58, 0x40040000);
+	out_be32(&sdram->cr59, 0xC0004004);
+	out_be32(&sdram->cr60, 0x0642C000);
+	out_be32(&sdram->cr61, 0x00000642);
+	asm("tpf");
+
+	out_be32(&sdram->cr09, 0x01000100);
+
+	udelay(100);
+#endif
+	return dramsize;
+};
+
+int testdram(void)
+{
+	return 0;
+}
diff --git a/board/c2mon/u-boot.lds b/board/freescale/m54418twr/u-boot.lds
index b9b8e3c..36a4c26 100644
--- a/board/c2mon/u-boot.lds
+++ b/board/freescale/m54418twr/u-boot.lds
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001-2010
+ * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -21,24 +21,14 @@
  * MA 02111-1307 USA
  */
 
-OUTPUT_ARCH(powerpc)
+OUTPUT_ARCH(m68k)
 
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
   .text      :
   {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    net/libnet.o			(.text*)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
+    arch/m68k/cpu/mcf5445x/start.o		(.text*)
 
     *(.text*)
   }
@@ -53,16 +43,18 @@ SECTIONS
   . = (. + 0x00FF) & 0xFFFFFF00;
   _erotext = .;
   PROVIDE (erotext = .);
+
   .reloc   :
   {
+    __got_start = .;
+    KEEP(*(.got))
+    __got_end = .;
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
   __fixup_entries = (. - _FIXUP_TABLE_)>>2;
 
   .data    :
@@ -74,10 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
@@ -92,12 +85,14 @@ SECTIONS
   __init_end = .;
 
   __bss_start = .;
-  .bss (NOLOAD)       :
+  .bss  (NOLOAD)     :
   {
+   _sbss = .;
    *(.bss*)
    *(.sbss*)
    *(COMMON)
    . = ALIGN(4);
+   _ebss = .;
   }
   __bss_end__ = . ;
   PROVIDE (end = .);
diff --git a/board/freescale/m54451evb/u-boot.lds b/board/freescale/m54451evb/u-boot.lds
index 45924b7..91328a4 100644
--- a/board/freescale/m54451evb/u-boot.lds
+++ b/board/freescale/m54451evb/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds
index f341449..36a4c26 100644
--- a/board/freescale/m54455evb/u-boot.lds
+++ b/board/freescale/m54455evb/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds
index 5472689..de4d0eb 100644
--- a/board/freescale/m547xevb/u-boot.lds
+++ b/board/freescale/m547xevb/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds
index cf3f38c..fbbe0c5 100644
--- a/board/freescale/m548xevb/u-boot.lds
+++ b/board/freescale/m548xevb/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 730ec4e..1071803 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -70,22 +70,22 @@ int checkboard(void)
 #ifndef CONFIG_NAND_SPL
 static struct pci_region pci_regions[] = {
 	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+		.size = CONFIG_SYS_PCI1_MEM_SIZE,
+		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
+		.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+		.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+		.size = CONFIG_SYS_PCI1_MMIO_SIZE,
+		.flags = PCI_REGION_MEM
 	},
 	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
+		.bus_start = CONFIG_SYS_PCI1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+		.size = CONFIG_SYS_PCI1_IO_SIZE,
+		.flags = PCI_REGION_IO
 	}
 };
 
diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
index 30676e1..2a172cc 100644
--- a/board/freescale/mpc8568mds/bcsr.c
+++ b/board/freescale/mpc8568mds/bcsr.c
@@ -25,7 +25,7 @@
 
 #include "bcsr.h"
 
-void enable_8568mds_duart()
+void enable_8568mds_duart(void)
 {
 	volatile uint* duart_mux	= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
 	volatile uint* devices		= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
@@ -36,21 +36,21 @@ void enable_8568mds_duart()
 	bcsr[5] |= 0x01;		/* Enable Duart in BCSR*/
 }
 
-void enable_8568mds_flash_write()
+void enable_8568mds_flash_write(void)
 {
 	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
 	bcsr[9] |= 0x01;
 }
 
-void disable_8568mds_flash_write()
+void disable_8568mds_flash_write(void)
 {
 	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
 	bcsr[9] &= ~(0x01);
 }
 
-void enable_8568mds_qe_mdio()
+void enable_8568mds_qe_mdio(void)
 {
 	u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
index b688e5c..37d0c5f 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -25,17 +25,17 @@
 
 #include "bcsr.h"
 
-void enable_8569mds_flash_write()
+void enable_8569mds_flash_write(void)
 {
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
 }
 
-void disable_8569mds_flash_write()
+void disable_8569mds_flash_write(void)
 {
 	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
 }
 
-void enable_8569mds_qe_uec()
+void enable_8569mds_qe_uec(void)
 {
 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
@@ -60,7 +60,7 @@ void enable_8569mds_qe_uec()
 #endif
 }
 
-void disable_8569mds_brd_eeprom_write_protect()
+void disable_8569mds_brd_eeprom_write_protect(void)
 {
 	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
 }
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 91ffdbe..5267729 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -57,9 +57,11 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
diff --git a/board/sbc8560/Makefile b/board/freescale/t4qds/Makefile
index ce01560..ff09ffa 100644
--- a/board/sbc8560/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -1,9 +1,5 @@
 #
-# (C) Copyright 2004-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
-# Added support for Wind River SBC8560 board
+# Copyright 2012 Freescale Semiconductor, Inc.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -15,7 +11,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -29,9 +25,11 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-$(CONFIG_T4240QDS)+= eth.o
+COBJS-$(CONFIG_PCI)	+= pci.o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
@@ -40,6 +38,12 @@ SOBJS	:= $(addprefix $(obj),$(SOBJS))
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
new file mode 100644
index 0000000..692616a
--- /dev/null
+++ b/board/freescale/t4qds/ddr.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{2,  1350,    5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{2,  2140,    5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{1,  1350,    5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900,    4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140,    4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{4,  1350,    5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
+	{4,  1666,    5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
+	{4,  2140,    5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
+	{2,  1350,    5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{2,  2140,    5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{1,  1350,    5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900,    4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140,    4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{}
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[0];
+	else
+		pbsp = udimms[0];
+
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->twoT_en = pbsp->force_2T;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+		popts->twoT_en = pbsp_highest->force_2T;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
new file mode 100644
index 0000000..a49c7d4
--- /dev/null
+++ b/board/freescale/t4qds/eth.c
@@ -0,0 +1,495 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+
+#include "t4240qds_qixis.h"
+
+#define EMI_NONE	0xFFFFFFFF
+#define EMI1_RGMII	0
+#define EMI1_SLOT1	1
+#define EMI1_SLOT2	2
+#define EMI1_SLOT3	3
+#define EMI1_SLOT4	4
+#define EMI1_SLOT5	5
+#define EMI1_SLOT7	7
+#define EMI2		8 /* tmp, FIXME */
+/* Slot6 and Slot8 do not have EMI connections */
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char *mdio_names[] = {
+	"T4240QDS_MDIO0",
+	"T4240QDS_MDIO1",
+	"T4240QDS_MDIO2",
+	"T4240QDS_MDIO3",
+	"T4240QDS_MDIO4",
+	"T4240QDS_MDIO5",
+	"NULL",
+	"T4240QDS_MDIO7",
+	"T4240QDS_10GC",
+};
+
+static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
+static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
+
+static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name = t4240qds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+struct t4240qds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static void t4240qds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+	if ((muxval < 6) || (muxval == 7)) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+				int regnum)
+{
+	struct t4240qds_mdio *priv = bus->priv;
+
+	t4240qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+				int regnum, u16 value)
+{
+	struct t4240qds_mdio *priv = bus->priv;
+
+	t4240qds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t4240qds_mdio_reset(struct mii_dev *bus)
+{
+	struct t4240qds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int t4240qds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct t4240qds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate T4240QDS MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate T4240QDS private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = t4240qds_mdio_read;
+	bus->write = t4240qds_mdio_write;
+	bus->reset = t4240qds_mdio_reset;
+	sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
+				enum fm_port port, int offset)
+{
+	if (mdio_mux[port] == EMI1_RGMII)
+		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
+
+	/* TODO: will do with dts */
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	/* TODO: will do with dts */
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+	int i;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1, srds_prtcl_s2;
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+					FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
+	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+	t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+	t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+
+	switch (srds_prtcl_s1) {
+	case 1:
+	case 2:
+	case 4:
+		/* XAUI/HiGig in Slot1 and Slot2 */
+		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+		break;
+	case 28:
+	case 36:
+		/* SGMII in Slot1 and Slot2 */
+		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+			fm_info_set_phy_address(FM1_DTSEC9,
+						SGMII_CARD_PORT4_PHY_ADDR);
+			fm_info_set_phy_address(FM1_DTSEC10,
+						SGMII_CARD_PORT3_PHY_ADDR);
+		}
+		break;
+	case 38:
+		fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
+		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+			fm_info_set_phy_address(FM1_DTSEC9,
+						QSGMII_CARD_PHY_ADDR);
+			fm_info_set_phy_address(FM1_DTSEC10,
+						QSGMII_CARD_PHY_ADDR);
+		}
+		break;
+	case 40:
+	case 46:
+	case 48:
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+			fm_info_set_phy_address(FM1_DTSEC10,
+						SGMII_CARD_PORT3_PHY_ADDR);
+			fm_info_set_phy_address(FM1_DTSEC9,
+						SGMII_CARD_PORT4_PHY_ADDR);
+		}
+		fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		break;
+	default:
+		puts("Invalid SerDes1 protocol for T4240QDS\n");
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1, lane, slot;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+						SGMII_FM1_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot_fsm1[lane];
+			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+				idx + 1, slot);
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			};
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			/* FM1 DTSEC5 routes to RGMII with EC2 */
+			debug("FM1@DTSEC%u is RGMII at address %u\n",
+				idx + 1, 2);
+			if (i == FM1_DTSEC5)
+				fm_info_set_phy_address(i, 2);
+			mdio_mux[i] = EMI1_RGMII;
+			fm_info_set_mdio(i,
+				mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			mdio_mux[i] = EMI2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	switch (srds_prtcl_s2) {
+	case 1:
+	case 2:
+	case 4:
+		/* XAUI/HiGig in Slot3 and Slot4 */
+		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
+		break;
+	case 7:
+	case 13:
+	case 14:
+	case 16:
+	case 22:
+	case 23:
+	case 25:
+	case 26:
+		/* XAUI/HiGig in Slot3, SGMII in Slot4 */
+		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	case 28:
+	case 36:
+		/* SGMII in Slot3 and Slot4 */
+		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		break;
+	case 38:
+		/* QSGMII in Slot3 and Slot4 */
+		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
+		break;
+	case 40:
+	case 46:
+	case 48:
+		/* SGMII in Slot3 */
+		fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		/* QSGMII in Slot4 */
+		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		break;
+	case 50:
+	case 52:
+	case 54:
+		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		break;
+	case 56:
+	case 57:
+		/* XFI in Slot3, SGMII in Slot4 */
+		fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		break;
+	default:
+		puts("Invalid SerDes2 protocol for T4240QDS\n");
+		break;
+	}
+
+	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+		int idx = i - FM2_DTSEC1, lane, slot;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_2,
+						SGMII_FM2_DTSEC1 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot_fsm2[lane];
+			debug("FM2@DTSEC%u expects SGMII in slot %u\n",
+				idx + 1, slot);
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+			switch (slot) {
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			case 4:
+				mdio_mux[i] = EMI1_SLOT4;
+				fm_info_set_mdio(i,
+					mii_dev_for_muxval(mdio_mux[i]));
+				break;
+			};
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			/*
+			 * If DTSEC5 is RGMII, then it's routed via via EC1 to
+			 * the first on-board RGMII port.  If DTSEC6 is RGMII,
+			 * then it's routed via via EC2 to the second on-board
+			 * RGMII port.
+			 */
+			debug("FM2@DTSEC%u is RGMII at address %u\n",
+				idx + 1, i == FM2_DTSEC5 ? 1 : 2);
+			fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
+			mdio_mux[i] = EMI1_RGMII;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			mdio_mux[i] = EMI2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
new file mode 100644
index 0000000..5debcf6
--- /dev/null
+++ b/board/freescale/t4qds/law.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/bmw/m48t59y.h b/board/freescale/t4qds/pci.c
index 717300d..fc00b4a 100644
--- a/board/bmw/m48t59y.h
+++ b/board/freescale/t4qds/pci.c
@@ -1,12 +1,5 @@
 /*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
- *
- * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -27,31 +20,20 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __M48_T59_Y_H
-#define __M48_T59_Y_H
-
-/*
- * M48 T59Y -Timekeeping Battery backed SRAM.
- */
-
-int m48_tod_init(void);
-
-int m48_tod_set(int year,
-		int month,
-		int day,
-		int hour,
-		int minute,
-		int second);
-
-int m48_tod_get(int *year,
-		int *month,
-		int *day,
-		int *hour,
-		int *minute,
-		int *second);
-
-int m48_tod_get_second(void);
-
-void m48_watchdog_arm(int usec);
-
-#endif /*!__M48_T59_Y_H */
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h
new file mode 100644
index 0000000..efb718d
--- /dev/null
+++ b/board/freescale/t4qds/t4240qds_qixis.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __T4020QDS_QIXIS_H__
+#define __T4020QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T4020QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xE0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+#define BRDCFG5_RESET			0x00
+
+#define BRDCFG12_SD3EN_MASK		0x20
+#define BRDCFG12_SD3MX_MASK		0x08
+#define BRDCFG12_SD3MX_SLOT5		0x08
+#define BRDCFG12_SD3MX_SLOT6		0x00
+#define BRDCFG12_SD4EN_MASK		0x04
+#define BRDCFG12_SD4MX_MASK		0x03
+#define BRDCFG12_SD4MX_SLOT7		0x02
+#define BRDCFG12_SD4MX_SLOT8		0x01
+#define BRDCFG12_SD4MX_AURO_SATA	0x00
+#endif
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
new file mode 100644
index 0000000..88b8ced
--- /dev/null
+++ b/board/freescale/t4qds/t4qds.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "t4qds.h"
+#include "t4240qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	u8 sw;
+	struct cpu_type *cpu = gd->cpu;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	unsigned int i;
+
+	printf("Board: %sQDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("Promjet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	/* Display the RCW, so that no one gets confused as to what RCW
+	 * we're actually using for this boot.
+	 */
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_be32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %08x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference Clocks: ");
+	sw = QIXIS_READ(brdcfg[2]);
+	for (i = 0; i < MAX_SERDES; i++) {
+		static const char *freq[] = {
+			"100", "125", "156.25", "161.1328125"};
+		unsigned int clock = (sw >> (2 * i)) & 3;
+
+		printf("SERDES%u=%sMHz ", i+1, freq[clock]);
+	}
+	puts("\n");
+
+	return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/* Configure Crossbar switches for Front-Side SerDes Ports */
+int config_frontside_crossbar_vsc3316(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1, srds_prtcl_s2;
+	int ret;
+
+	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
+	if (ret)
+		return ret;
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+	if (srds_prtcl_s1) {
+		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
+		if (ret)
+			return ret;
+		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
+		if (ret)
+			return ret;
+	}
+
+	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	if (srds_prtcl_s2) {
+		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
+		if (ret)
+			return ret;
+		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int config_backside_crossbar_mux(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s3, srds_prtcl_s4;
+	u8 brdcfg;
+
+	srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
+	srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
+	switch (srds_prtcl_s3) {
+	case 0:
+		/* SerDes3 is not enabled */
+		break;
+	case 2:
+	case 9:
+	case 10:
+		/* SD3(0:7) => SLOT5(0:7) */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD3MX_MASK;
+		brdcfg |= BRDCFG12_SD3MX_SLOT5;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	case 4:
+	case 6:
+	case 8:
+	case 12:
+	case 14:
+	case 16:
+	case 17:
+	case 19:
+	case 20:
+		/* SD3(4:7) => SLOT6(0:3) */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD3MX_MASK;
+		brdcfg |= BRDCFG12_SD3MX_SLOT6;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	default:
+		printf("WARNING: unsupported for SerDes3 Protocol %d\n",
+				srds_prtcl_s3);
+		return -1;
+	}
+
+	srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
+	srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
+	switch (srds_prtcl_s4) {
+	case 0:
+		/* SerDes4 is not enabled */
+		break;
+	case 2:
+		/* 10b, SD4(0:7) => SLOT7(0:7) */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD4MX_MASK;
+		brdcfg |= BRDCFG12_SD4MX_SLOT7;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	case 4:
+	case 6:
+	case 8:
+		/* x1b, SD4(4:7) => SLOT8(0:3) */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD4MX_MASK;
+		brdcfg |= BRDCFG12_SD4MX_SLOT8;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	case 10:
+	case 12:
+	case 14:
+	case 16:
+	case 18:
+		/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
+		brdcfg = QIXIS_READ(brdcfg[12]);
+		brdcfg &= ~BRDCFG12_SD4MX_MASK;
+		brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
+		QIXIS_WRITE(brdcfg[12], brdcfg);
+		break;
+	default:
+		printf("WARNING: unsupported for SerDes4 Protocol %d\n",
+				srds_prtcl_s4);
+		return -1;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	/* Disable remote I2C connectoin */
+	QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
+
+	/* Configure board SERDES ports crossbar */
+	config_frontside_crossbar_vsc3316();
+	config_backside_crossbar_mux();
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	case SRDS_PLLCR0_RFCK_SEL_161_13:
+		return "161.1328125";
+	default:
+		return "???";
+	}
+}
+
+int misc_init_r(void)
+{
+	u8 sw;
+	serdes_corenet_t *srds_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[MAX_SERDES];
+	unsigned int i;
+
+	sw = QIXIS_READ(brdcfg[2]);
+	for (i = 0; i < MAX_SERDES; i++) {
+		unsigned int clock = (sw >> (2 * i)) & 3;
+		switch (clock) {
+		case 0:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+			break;
+		case 1:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+			break;
+		case 2:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+			break;
+		case 3:
+			actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
+			break;
+		}
+	}
+
+	for (i = 0; i < MAX_SERDES; i++) {
+		u32 pllcr0 = srds_regs->bank[i].pllcr0;
+		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES%u expects reference clock"
+			       " %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+	fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}
diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h
new file mode 100644
index 0000000..c6a3492
--- /dev/null
+++ b/board/freescale/t4qds/t4qds.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+				{8, 8}, {9, 9}, {14, 14}, {15, 15} };
+
+static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+				{10, 10}, {11, 11}, {12, 12}, {13, 13} };
+
+static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+				{10, 11}, {11, 10}, {12, 2}, {13, 3} };
+
+static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+				{8, 9}, {9, 8}, {14, 1}, {15, 0} };
+#endif
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
new file mode 100644
index 0000000..078a6e4
--- /dev/null
+++ b/board/freescale/t4qds/tlb.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 16, BOOKE_PAGESZ_1M, 1),
+#endif
+	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 17, BOOKE_PAGESZ_4K, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds
index 87cb8e3..774c494 100644
--- a/board/gaisler/gr_cpci_ax2000/u-boot.lds
+++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds
@@ -85,10 +85,11 @@ SECTIONS
 
 	/* CMD Table */
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
+
 	. = ALIGN(4);
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	.data	:
 	{
diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds
index 2fb44aa..f6d1301 100644
--- a/board/gaisler/gr_ep2s60/u-boot.lds
+++ b/board/gaisler/gr_ep2s60/u-boot.lds
@@ -85,10 +85,11 @@ SECTIONS
 
 	/* CMD Table */
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
+
 	. = ALIGN(4);
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	.data	:
 	{
diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds
index 8719e97..7df6e83 100644
--- a/board/gaisler/gr_xc3s_1500/u-boot.lds
+++ b/board/gaisler/gr_xc3s_1500/u-boot.lds
@@ -85,10 +85,11 @@ SECTIONS
 
 	/* CMD Table */
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
+
 	. = ALIGN(4);
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	.data	:
 	{
diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds
index 33890b5..b241cbc 100644
--- a/board/gaisler/grsim/u-boot.lds
+++ b/board/gaisler/grsim/u-boot.lds
@@ -84,10 +84,11 @@ SECTIONS
 
 	/* CMD Table */
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
+
 	. = ALIGN(4);
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	.data	:
 	{
diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds
index cf6e502..63c15b9 100644
--- a/board/gaisler/grsim_leon2/u-boot.lds
+++ b/board/gaisler/grsim_leon2/u-boot.lds
@@ -84,10 +84,11 @@ SECTIONS
 
 	/* CMD Table */
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
+
 	. = ALIGN(4);
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	.data	:
 	{
diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds
index 5bb6c62..1cbe7e3 100644
--- a/board/gen860t/u-boot-flashenv.lds
+++ b/board/gen860t/u-boot-flashenv.lds
@@ -71,9 +71,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  .u_boot_list : {
+		#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds
index be99b51..dd89c70 100644
--- a/board/gen860t/u-boot.lds
+++ b/board/gen860t/u-boot.lds
@@ -71,9 +71,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds
index 1d66a9b..124b183 100644
--- a/board/genietv/u-boot.lds
+++ b/board/genietv/u-boot.lds
@@ -80,9 +80,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug
index cfa4ef3..e1cf249 100644
--- a/board/genietv/u-boot.lds.debug
+++ b/board/genietv/u-boot.lds.debug
@@ -107,9 +107,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/c2mon/Makefile b/board/h2200/Makefile
index b49f26d..51b1a9e 100644
--- a/board/c2mon/Makefile
+++ b/board/h2200/Makefile
@@ -1,9 +1,7 @@
 #
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# h2200 Support
 #
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
@@ -25,11 +23,18 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	= $(BOARD).o flash.o pcmcia.o
+COBJS	:= h2200.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c) h2200-header.S
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all: $(LIB) $(obj)h2200-header.bin
+
+$(obj)h2200-header.o: h2200-header.S
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+$(obj)h2200-header.bin: $(obj)h2200-header.o
+	$(OBJCOPY) -O binary $< $@
 
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
diff --git a/board/h2200/h2200-header.S b/board/h2200/h2200-header.S
new file mode 100644
index 0000000..c335bfe
--- /dev/null
+++ b/board/h2200/h2200-header.S
@@ -0,0 +1,27 @@
+/*
+ * iPAQ h2200 header
+ *
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+	.word 0xea0003fe /* b 0x1000 */
+
+	.org 0x40
+	.ascii "ECEC"
+
+	.org 0x1000 - 1
+	.byte 0x0
diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c
new file mode 100644
index 0000000..3076306
--- /dev/null
+++ b/board/h2200/h2200.c
@@ -0,0 +1,53 @@
+/*
+ * iPAQ h2200 board configuration
+ *
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	gd->bd->bi_arch_number = MACH_TYPE_H2200;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/*
+	 * Everything except MSC0 was already set up by
+	 * 1st stage bootloader.
+	 *
+	 * This setting enables access to companion chip.
+	 */
+	clrsetbits_le32(MSC0, 0xffffffff, CONFIG_SYS_MSC0_VAL);
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds
index ca97115..f02eb1c 100644
--- a/board/hermes/u-boot.lds
+++ b/board/hermes/u-boot.lds
@@ -72,9 +72,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug
index 8a197de..e84cc79 100644
--- a/board/hermes/u-boot.lds.debug
+++ b/board/hermes/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 7c9d34a..9fe6408 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -27,6 +27,8 @@
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/omap_gpio.h>
+#include <asm/arch/dss.h>
+#include <asm/arch/clocks.h>
 #include "errno.h"
 #include <i2c.h>
 #ifdef CONFIG_USB_EHCI
@@ -37,12 +39,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define HOT_WATER_BUTTON	38
+#define HOT_WATER_BUTTON	42
+#define LCD_OUTPUT		55
+
+/* Address of the framebuffer in RAM. */
+#define FB_START_ADDRESS 0x88000000
 
 #ifdef CONFIG_USB_EHCI
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 };
 
@@ -67,6 +73,8 @@ int board_init(void)
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
+	gpio_direction_output(LCD_OUTPUT, 0);
+
 	return 0;
 }
 
@@ -87,6 +95,7 @@ int board_late_init(void)
 		return 0;
 
 	setenv("bootcmd", "run swupdate");
+
 	return 0;
 }
 #endif
@@ -109,15 +118,34 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI_OMAP
-#define USB_HOST_PWR_EN		132
-int board_usb_init(void)
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+
+static struct panel_config lcd_cfg = {
+	.timing_h       = PANEL_TIMING_H(40, 40, 48),
+	.timing_v       = PANEL_TIMING_V(29, 13, 3),
+	.pol_freq       = 0x00003000, /* Pol Freq */
+	.divisor        = 0x0001000E,
+	.panel_type     = 0x01, /* TFT */
+	.data_lines     = 0x03, /* 24 Bit RGB */
+	.load_mode      = 0x02, /* Frame Mode */
+	.panel_color	= 0,
+	.lcd_size	= PANEL_LCD_SIZE(800, 480),
+};
+
+int board_video_init(void)
 {
-	if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
-		puts("Failed to get USB_HOST_PWR_EN pin\n");
-		return -ENODEV;
-	}
-	gpio_direction_output(USB_HOST_PWR_EN, 1);
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	void *fb;
+
+	fb = (void *)FB_START_ADDRESS;
+
+	lcd_cfg.frame_buffer = fb;
+
+	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
+
+	omap3_dss_panel_config(&lcd_cfg);
+	omap3_dss_enable();
 
 	return 0;
 }
diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h
index 867cc9e..0d4c642 100644
--- a/board/htkw/mcx/mcx.h
+++ b/board/htkw/mcx/mcx.h
@@ -96,7 +96,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(GPMC_A7),		(IEN | PTU | EN  | M4)) \
 	MUX_VAL(CP(GPMC_A8),		(IEN | PTU | EN  | M4)) \
 	MUX_VAL(CP(GPMC_A9),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | DIS | M4)) \
+	MUX_VAL(CP(GPMC_A10),		(IEN | PTU | EN | M4)) \
 					/* GPIO_43 LCD buffer enable */ \
 	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
 	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
@@ -143,28 +143,28 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA0),		(IEN | PTU | EN  | M4))\
-	MUX_VAL(CP(DSS_DATA1),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(DSS_DATA2),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA8),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(DSS_DATA9),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA16),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(DSS_DATA17),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(DSS_DATA18),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0))  \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
 	/* CAMERA */\
@@ -264,6 +264,8 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
 	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
 	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M4)) \
+					/* GPIO_170 Touchscreen ISR */\
 	/* McSPI */\
 	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
@@ -313,11 +315,11 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
 	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
 	/* HECC */\
-	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTD | EN  | M0)) \
 	/* HSUSB */\
 	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IEN  | PTU | DIS  | M0)) \
 	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds
index 1309f20..7afae0a 100644
--- a/board/hymod/u-boot.lds
+++ b/board/hymod/u-boot.lds
@@ -110,9 +110,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug
index 99c48f2..dc8c4e9 100644
--- a/board/hymod/u-boot.lds.debug
+++ b/board/hymod/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds
index 93c79a6..6778eb1 100644
--- a/board/icu862/u-boot.lds
+++ b/board/icu862/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug
index 91d3e67..3e075a8 100644
--- a/board/icu862/u-boot.lds.debug
+++ b/board/icu862/u-boot.lds.debug
@@ -107,9 +107,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds
index f697ccd..0d6a0f3 100644
--- a/board/idmr/u-boot.lds
+++ b/board/idmr/u-boot.lds
@@ -65,9 +65,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
index 4a59cea..8a871cf 100644
--- a/board/incaip/u-boot.lds
+++ b/board/incaip/u-boot.lds
@@ -54,10 +54,9 @@ SECTIONS
 
 	.sdata  : { *(.sdata*) }
 
-	.u_boot_cmd : {
-	  __u_boot_cmd_start = .;
-	  *(.u_boot_cmd)
-	  __u_boot_cmd_end = .;
+	. = ALIGN(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
 
 	uboot_end_data = .;
diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/ip860/u-boot.lds
+++ b/board/ip860/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug
index 2f61b11..e47aff0 100644
--- a/board/ip860/u-boot.lds.debug
+++ b/board/ip860/u-boot.lds.debug
@@ -107,9 +107,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c
index 71d64d4..ab29479 100644
--- a/board/ivm/ivm.c
+++ b/board/ivm/ivm.c
@@ -333,13 +333,59 @@ void show_boot_progress (int status)
 void ide_set_reset (int on)
 {
 	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	int i;
 
 	/*
 	 * Configure PC for IDE Reset Pin
 	 */
 	if (on) {		/* assert RESET */
 		immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
+
+#ifdef CONFIG_SYS_PB_12V_ENABLE
+		/* 12V Enable output OFF */
+		immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
+
+		immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
+		immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
+		immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
+
+		/* wait 500 ms for the voltage to stabilize */
+		for (i = 0; i < 500; ++i)
+			udelay(1000);
+#endif /* CONFIG_SYS_PB_12V_ENABLE */
 	} else {		/* release RESET */
+#ifdef CONFIG_SYS_PB_12V_ENABLE
+		/* 12V Enable output ON */
+		immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
+#endif /* CONFIG_SYS_PB_12V_ENABLE */
+
+#ifdef CONFIG_SYS_PB_IDE_MOTOR
+		/* configure IDE Motor voltage monitor pin as input */
+		immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+		immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+		immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+
+/* wait up to 1 s for the motor voltage to stabilize */
+		for (i = 0; i < 1000; ++i) {
+			if ((immr->im_cpm.cp_pbdat
+					& CONFIG_SYS_PB_IDE_MOTOR) != 0)
+				break;
+			udelay(1000);
+		}
+
+		if (i == 1000) {	/* Timeout */
+			printf("\nWarning: 5V for IDE Motor missing\n");
+#ifdef CONFIG_STATUS_LED
+#ifdef STATUS_LED_YELLOW
+			status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
+#endif
+#ifdef STATUS_LED_GREEN
+			status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
+#endif
+#endif /* CONFIG_STATUS_LED */
+		}
+#endif /* CONFIG_SYS_PB_IDE_MOTOR */
+
 		immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
 	}
 
diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds
index 1e843eb..4cca652 100644
--- a/board/ivm/u-boot.lds
+++ b/board/ivm/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug
index 732a46f..53a19b2 100644
--- a/board/ivm/u-boot.lds.debug
+++ b/board/ivm/u-boot.lds.debug
@@ -107,9 +107,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index e01a633..83a8753 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{5,  2, 1, 0, 1}, /* UART2_RTS */
 	{5,  3, 2, 0, 2}, /* UART2_SIN */
 	{5,  1, 2, 0, 3}, /* UART2_CTS */
-#else
+#elif !defined(CONFIG_MPC8309)
 	/* Local Bus */
 	{0, 16, 1, 0, 3}, /* LA00 */
 	{0, 17, 1, 0, 3}, /* LA01 */
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
index 525c97a..54f25e0 100644
--- a/board/kmc/kzm9g/kzm9g.c
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SMSTPCR1_CMT0	(1 << 24)
 #define SMSTPCR1_I2C0	(1 << 16)
 #define SMSTPCR3_USB	(1 << 22)
+#define SMSTPCR3_I2C1	(1 << 23)
 
 #define PORT32CR (0xE6051020)
 #define PORT33CR (0xE6051021)
@@ -287,8 +288,8 @@ int board_early_init_f(void)
 
 	clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
 	clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
-	clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB);
-	clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB);
+	clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
+	clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
 	writel(VCLKCR1_D, &cpg->vclkcr1);
 
 	/* Setup SCIF4 / workaround */
@@ -343,6 +344,8 @@ int board_init(void)
 	gpio_direction_output(GPIO_PORT15, 1);
 
 	/* I2C */
+	gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
+	gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
 	gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
 	gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
 
diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds
index 6a017e3..033cff4 100644
--- a/board/korat/u-boot-F7FC.lds
+++ b/board/korat/u-boot-F7FC.lds
@@ -108,10 +108,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/kup/kup4k/u-boot.lds
+++ b/board/kup/kup4k/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug
index 4491edd..b43a1e4 100644
--- a/board/kup/kup4k/u-boot.lds.debug
+++ b/board/kup/kup4k/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/kup/kup4x/u-boot.lds
+++ b/board/kup/kup4x/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug
index 4491edd..b43a1e4 100644
--- a/board/kup/kup4x/u-boot.lds.debug
+++ b/board/kup/kup4x/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/lantec/flash.c b/board/lantec/flash.c
deleted file mode 100644
index 97ed054..0000000
--- a/board/lantec/flash.c
+++ /dev/null
@@ -1,625 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Derived from ../tqm8xx/flash.c
- * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG]
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0, size_b1;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0: "
-			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
-			flash_info[0].flash_id,
-			size_b0, size_b0<<20);
-	}
-
-	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE5_PRELIM);
-
-	size_b1 = flash_get_size((vu_long *)FLASH_BASE5_PRELIM, &flash_info[1]);
-
-	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	if (size_b1 > size_b0) {
-		printf ("## ERROR: "
-			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-			size_b1, size_b1<<20,
-			size_b0, size_b0<<20
-		);
-		flash_info[0].flash_id	= FLASH_UNKNOWN;
-		flash_info[1].flash_id	= FLASH_UNKNOWN;
-		flash_info[0].sector_count	= -1;
-		flash_info[1].sector_count	= -1;
-		flash_info[0].size		= 0;
-		flash_info[1].size		= 0;
-		return (0);
-	}
-
-	DEBUGF ("## Before remap: "
-		"BR0: 0x%08x    OR0: 0x%08x    "
-		"BR1: 0x%08x    OR1: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0,
-		memctl->memc_br1, memctl->memc_or1);
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
-				BR_MS_GPCM | BR_PS_32 | BR_V;
-
-	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0);
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-		      &flash_info[0]);
-#endif
-
-	if (size_b1) {
-		memctl->memc_or5 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br5 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
-				    BR_MS_GPCM | BR_PS_32 | BR_V;
-
-		DEBUGF("## BR5: 0x%08x    OR5: 0x%08x\n",
-			memctl->memc_br5, memctl->memc_or5);
-
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
-					  &flash_info[1]);
-
-		flash_info[1].size = size_b1;
-
-		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_SYS_MONITOR_BASE,
-			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[1]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-			      &flash_info[1]);
-#endif
-	} else {
-		memctl->memc_br5 = 0;		/* invalidate bank */
-		memctl->memc_or5 = 0;		/* invalidate bank */
-
-		DEBUGF("## DISABLE BR5: 0x%08x    OR5: 0x%08x\n",
-			memctl->memc_br5, memctl->memc_or5);
-
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-		flash_info[1].size = 0;
-	}
-
-	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	switch (value) {
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c
deleted file mode 100644
index 6d3486c..0000000
--- a/board/lantec/lantec.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2001
- * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
- * Bruno Achauer, Exet AG, bruno@exet-ag.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Derived from ../tqm8xx/tqm8xx.c
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-const uint sdram_table[] = {
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
-	0x1ff77c47,		/* last */
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-	0x1ff77c35, 0xefeabc34, 0x1fb57c35,	/* last */
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
-	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	/* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	/* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-	0xf0affc00, 0xe1bbbc04, 0x1ff77c47,	/* last */
-	_NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Refresh  (Offset 30 in UPMA RAM)
-	 */
-	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc84, 0xfffffc07, 0xfffffc07,	/* last */
-	_NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Exception. (Offset 3c in UPMA RAM)
-	 */
-	0x7ffffc07,		/* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test TQ ID string (TQM8xx...)
- * If present, check for "L" type (no second DRAM bank),
- * otherwise "L" type is assumed as default.
- *
- * Return 1 for "L" type, 0 else.
- */
-
-int checkboard (void)
-{
-	printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size_b0;
-	int i;
-
-	/*
-	 * Configure UPMA for SDRAM
-	 */
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ;
-
-	/* burst length=4, burst type=sequential, CAS latency=2 */
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller bank 3 to the SDRAM bank at preliminary address.
-	 */
-	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
-	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
-	/* initialize memory address register */
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */
-
-	/* mode initialization (offset 5) */
-	udelay (200);		/* 0x80006105 */
-	memctl->memc_mcr =
-		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
-
-	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
-	udelay (1);		/* 0x80006130 */
-	memctl->memc_mcr =
-		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
-	udelay (1);		/* 0x80006130 */
-	memctl->memc_mcr =
-		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
-
-	udelay (1);		/* 0x80006106 */
-	memctl->memc_mcr =
-		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
-
-	udelay (200);
-
-	/* Need at least 10 DRAM accesses to stabilize */
-	for (i = 0; i < 10; ++i) {
-		volatile unsigned long *addr =
-			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
-		unsigned long val;
-
-		val = *(addr + i);
-		*(addr + i) = val;
-	}
-
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 */
-	size_b0 = dram_size (CONFIG_SYS_MAMR_8COL,
-			     (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
-
-	/*
-	 * Final mapping:
-	 */
-
-	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-	udelay (1000);
-
-	return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-			   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size (base, maxsize));
-}
diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds
deleted file mode 100644
index de0b355..0000000
--- a/board/lantec/u-boot.lds
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    net/libnet.o			(.text*)
-    arch/powerpc/lib/libpowerpc.o	(.text*)
-    drivers/rtc/librtc.o		(.text*)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug
deleted file mode 100644
index 856a99b..0000000
--- a/board/lantec/u-boot.lds.debug
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c
index f3e3fce..541c958 100644
--- a/board/linkstation/ide.c
+++ b/board/linkstation/ide.c
@@ -37,7 +37,6 @@
 #define IT8212_PCI_IdeBusSkewCONTROL	0x4c
 #define IT8212_PCI_IdeDrivingCURRENT	0x42
 
-extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
 extern struct pci_controller hose;
 
 int ide_preinit (void)
diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c
index 3527b38..ef2cc24 100644
--- a/board/lubbock/lubbock.c
+++ b/board/lubbock/lubbock.c
@@ -29,6 +29,7 @@
 #include <netdev.h>
 #include <asm/arch/pxa.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/regs-mmc.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -56,6 +57,14 @@ int board_init (void)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
+
 int board_late_init(void)
 {
 	setenv("stdout", "serial");
diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds
index 8bf7324..bc71b0d 100644
--- a/board/lwmon/u-boot.lds
+++ b/board/lwmon/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug
index 2412234..0a3e646 100644
--- a/board/lwmon/u-boot.lds.debug
+++ b/board/lwmon/u-boot.lds.debug
@@ -107,9 +107,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds
index 731cec9..e32ae37 100644
--- a/board/manroland/uc100/u-boot.lds
+++ b/board/manroland/uc100/u-boot.lds
@@ -69,9 +69,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds
index 57c37de..5a3a9ea 100644
--- a/board/matrix_vision/mvsmr/u-boot.lds
+++ b/board/matrix_vision/mvsmr/u-boot.lds
@@ -74,9 +74,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/mbx8xx/u-boot.lds
+++ b/board/mbx8xx/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug
index a95c47f..4155b60 100644
--- a/board/mbx8xx/u-boot.lds.debug
+++ b/board/mbx8xx/u-boot.lds.debug
@@ -107,9 +107,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds
index 3a05ef9..2ce8d0e 100644
--- a/board/micronas/vct/u-boot.lds
+++ b/board/micronas/vct/u-boot.lds
@@ -53,10 +53,8 @@ SECTIONS
 	.sdata  : { *(.sdata*) }
 
 	. = ALIGN(4);
-	.u_boot_cmd : {
-	  __u_boot_cmd_start = .;
-	  *(.u_boot_cmd)
-	  __u_boot_cmd_end = .;
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
 
 	. = ALIGN(4);
diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds
index dae2cfc..43f91f1 100644
--- a/board/mousse/u-boot.lds
+++ b/board/mousse/u-boot.lds
@@ -60,9 +60,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram
index b3364be..5255651 100644
--- a/board/mousse/u-boot.lds.ram
+++ b/board/mousse/u-boot.lds.ram
@@ -85,9 +85,6 @@ SECTIONS
   } > ram
   */
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
    __start___ex_table = .;
     __ex_table : { *(__ex_table) } > ram
diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom
index b4b9e02..29a34fb 100644
--- a/board/mousse/u-boot.lds.rom
+++ b/board/mousse/u-boot.lds.rom
@@ -102,9 +102,6 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
   __start___ex_table = .;
   __ex_table : { *(__ex_table) }
diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug
index fcf8ebb..d7a2e56 100644
--- a/board/mpl/pip405/u-boot.lds.debug
+++ b/board/mpl/pip405/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds
index 11624d2..c378564 100644
--- a/board/mvblue/u-boot.lds
+++ b/board/mvblue/u-boot.lds
@@ -70,9 +70,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds
index a949e4f..cdc1fda 100644
--- a/board/netphone/u-boot.lds
+++ b/board/netphone/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug
index a001f3f..900da64 100644
--- a/board/netphone/u-boot.lds.debug
+++ b/board/netphone/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds
index a949e4f..cdc1fda 100644
--- a/board/netta/u-boot.lds
+++ b/board/netta/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug
index a001f3f..900da64 100644
--- a/board/netta/u-boot.lds.debug
+++ b/board/netta/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds
index a949e4f..cdc1fda 100644
--- a/board/netta2/u-boot.lds
+++ b/board/netta2/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug
index a001f3f..900da64 100644
--- a/board/netta2/u-boot.lds.debug
+++ b/board/netta2/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds
index a949e4f..cdc1fda 100644
--- a/board/netvia/u-boot.lds
+++ b/board/netvia/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug
index 6c7d698..6cbf4dc 100644
--- a/board/netvia/u-boot.lds.debug
+++ b/board/netvia/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/etx094/Makefile b/board/nokia/rx51/Makefile
index 6dc495c..86fb48c 100644
--- a/board/etx094/Makefile
+++ b/board/nokia/rx51/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2006
+# (C) Copyright 2000, 2001, 2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -25,11 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	= $(BOARD).o flash.o
+COBJS-y	:= $(BOARD).o
+SOBJS-y := lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+COBJS	:= $(sort $(COBJS-y))
+SOBJS	:= $(sort $(SOBJS-y))
+SRCS	:= $(COBJS:.o=.c) $(SOBJS:.o=.S)
+OBJS	:= $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S
new file mode 100644
index 0000000..055b103
--- /dev/null
+++ b/board/nokia/rx51/lowlevel_init.S
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+relocaddr:		/* address of this relocaddr section after coping */
+	.word .		/* address of section (calculated at compile time) */
+
+startaddr:		/* address of u-boot after copying */
+	.word CONFIG_SYS_TEXT_BASE
+
+kernaddr:		/* address of kernel after copying */
+	.word KERNEL_ADDRESS
+
+kernsize:		/* maximal size of kernel image */
+	.word KERNEL_MAXSIZE
+
+kernoffs:		/* offset of kernel image in loaded u-boot */
+	.word KERNEL_OFFSET
+
+imagesize:		/* maximal size of image */
+	.word IMAGE_MAXSIZE
+
+ih_magic:		/* IH_MAGIC in big endian from include/image.h */
+	.word 0x56190527
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: Copy attached kernel to address KERNEL_ADDRESS
+ *              Copy u-boot to address CONFIG_SYS_TEXT_BASE
+ *              Return to copied u-boot address
+ */
+
+.global save_boot_params
+save_boot_params:
+
+
+/* Copy valid attached kernel to address KERNEL_ADDRESS */
+
+copy_kernel_start:
+	adr	r0, relocaddr	/* r0 - address of section relocaddr */
+	ldr	r1, relocaddr	/* r1 - address of relocaddr after relocation */
+	cmp	r0, r1
+
+	/* r4 - calculated offset */
+	subhi	r4, r0, r1
+	sublo	r4, r1, r0
+
+	/* r0 - start of kernel before */
+	ldr	r0, startaddr
+	addhi	r0, r0, r4
+	sublo	r0, r0, r4
+	ldr	r1, kernoffs
+	add	r0, r0, r1
+
+	/* r3 - start of kernel after */
+	ldr	r3, kernaddr
+
+	/* r2 - end of kernel after */
+	ldr	r1, kernsize
+	add	r2, r3, r1
+
+	/* r1 - end of kernel before */
+	add	r1, r0, r1
+
+	/* remove header in target kernel */
+	mov	r5, #0
+	str	r5, [r3]
+
+	/* check for valid kernel uImage */
+	ldr	r4, [r0]	/* r4 - 4 bytes header of kernel */
+	ldr	r5, ih_magic	/* r5 - IH_MAGIC */
+	cmp	r4, r5
+	bne	copy_kernel_end	/* skip if invalid image */
+
+copy_kernel_loop:
+	ldmdb	r1!, {r3 - r10}
+	stmdb	r2!, {r3 - r10}
+	cmp	r1, r0
+	bhi	copy_kernel_loop
+
+copy_kernel_end:
+	mov	r5, #0
+	str	r5, [r0]	/* remove 4 bytes header of kernel */
+
+
+/* Fix u-boot code */
+
+fix_start:
+	adr	r0, relocaddr	/* r0 - address of section relocaddr */
+	ldr	r1, relocaddr	/* r1 - address of relocaddr after relocation */
+	cmp	r0, r1
+
+	beq	copy_uboot_end	/* skip if u-boot is on correct address */
+
+	/* r5 - calculated offset */
+	subhi	r5, r0, r1
+	sublo	r5, r1, r0
+
+	/* r6 - maximal u-boot size */
+	ldr	r6, imagesize
+
+	/* fix return address */
+	subhi	lr, lr, r5
+	addlo	lr, lr, r5
+
+	/* r1 - start of u-boot after */
+	ldr	r1, startaddr
+
+	/* r0 - start of u-boot before */
+	addhi	r0, r1, r5
+	sublo	r0, r1, r5
+
+	/* check if we need to move uboot copy code before calling it */
+	cmp	r5, r6
+	bhi	copy_uboot_start /* now coping u-boot code directly is safe */
+
+
+copy_code_start:
+	/* r0 - start of u-boot before */
+	/* r1 - start of u-boot after */
+	/* r6 - maximal u-boot size */
+
+	/* r7 - maximal kernel size */
+	ldr	r7, kernsize
+
+	/* r4 - end of kernel before */
+	add	r4, r0, r6
+	add	r4, r4, r7
+
+	/* r5 - end of u-boot after */
+	ldr	r5, startaddr
+	add	r5, r5, r6
+
+	/* r2 - start of loop code after */
+	cmp	r4, r5		/* higher address (r4 or r5) */
+	movhs	r2, r4
+	movlo	r2, r5
+
+	/* r3 - end of loop code before */
+	adr	r3, end
+
+	/* r4 - end of loop code after */
+	adr	r4, copy_uboot_start
+	sub	r4, r3, r4
+	add	r4, r2, r4
+
+copy_code_loop:
+	ldmdb	r3!, {r7 - r10}
+	stmdb	r4!, {r7 - r10}
+	cmp	r4, r2
+	bhi	copy_code_loop
+
+copy_code_end:
+	mov	pc, r2
+
+
+/* Copy u-boot to address CONFIG_SYS_TEXT_BASE */
+
+copy_uboot_start:
+	/* r0 - start of u-boot before */
+	/* r1 - start of u-boot after */
+	/* r6 - maximal u-boot size */
+
+	/* r2 - end of u-boot after */
+	add	r2, r1, r6
+
+	/* condition for copying from left to right */
+	cmp	r0, r1
+	addlo	r1, r0, r6	/* r1 - end of u-boot before */
+	blo	copy_uboot_loop_right
+
+copy_uboot_loop_left:
+	ldmia	r0!, {r3 - r10}
+	stmia	r1!, {r3 - r10}
+	cmp	r1, r2
+	blo	copy_uboot_loop_left
+	b	copy_uboot_end
+
+copy_uboot_loop_right:
+	ldmdb	r1!, {r3 - r10}
+	stmdb	r2!, {r3 - r10}
+	cmp	r1, r0
+	bhi	copy_uboot_loop_right
+
+copy_uboot_end:
+	bx	lr
+
+end:
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
new file mode 100644
index 0000000..b2fe1c5
--- /dev/null
+++ b/board/nokia/rx51/rx51.c
@@ -0,0 +1,677 @@
+/*
+ * (C) Copyright 2012
+ * Ивайло Димитров <freemangordon@abv.bg>
+ *
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2010
+ * Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code:
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <malloc.h>
+#include <twl4030.h>
+#include <i2c.h>
+#include <video_fb.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/bitops.h>
+#include <asm/mach-types.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "rx51.h"
+#include "tag_omap.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+GraphicDevice gdev;
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"Nokia RX-51",
+	"OneNAND"
+};
+
+/* This structure contains default omap tags needed for booting Maemo 5 */
+static struct tag_omap omap[] = {
+	OMAP_TAG_UART_CONFIG(0x04),
+	OMAP_TAG_SERIAL_CONSOLE_CONFIG(0x03, 0x01C200),
+	OMAP_TAG_LCD_CONFIG("acx565akm", "internal", 90, 0x18),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cam_focus", 0x44, 0x1, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cam_launch", 0x45, 0x1, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cam_shutter", 0x6e, 0x1, 0x0, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_apeslpx", 0x46, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_bsi", 0x9d, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_en", 0x4a, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst", 0x4b, 0x6, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst_rq", 0x49, 0x6, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_wddis", 0x0d, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("headphone", 0xb1, 0x1, 0x1, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("kb_lock", 0x71, 0x1, 0x0, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("proximity", 0x59, 0x0, 0x0, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("sleep_ind", 0xa2, 0x2, 0x2, 0x0),
+	OMAP_TAG_GPIO_SWITCH_CONFIG("slide", GPIO_SLIDE, 0x0, 0x0, 0x0),
+	OMAP_TAG_WLAN_CX3110X_CONFIG(0x25, 0xff, 87, 42, -1),
+	OMAP_TAG_PARTITION_CONFIG(PART1_NAME, PART1_SIZE * PART1_MULL,
+			PART1_OFFS, PART1_MASK),
+	OMAP_TAG_PARTITION_CONFIG(PART2_NAME, PART2_SIZE * PART2_MULL,
+			PART2_OFFS, PART2_MASK),
+	OMAP_TAG_PARTITION_CONFIG(PART3_NAME, PART3_SIZE * PART3_MULL,
+			PART3_OFFS, PART3_MASK),
+	OMAP_TAG_PARTITION_CONFIG(PART4_NAME, PART4_SIZE * PART4_MULL,
+			PART4_OFFS, PART4_MASK),
+	OMAP_TAG_PARTITION_CONFIG(PART5_NAME, PART5_SIZE * PART5_MULL,
+			PART5_OFFS, PART5_MASK),
+	OMAP_TAG_PARTITION_CONFIG(PART6_NAME, PART6_SIZE * PART6_MULL,
+			PART6_OFFS, PART6_MASK),
+	OMAP_TAG_BOOT_REASON_CONFIG("pwr_key"),
+	OMAP_TAG_VERSION_STR_CONFIG("product", "RX-51"),
+	OMAP_TAG_VERSION_STR_CONFIG("hw-build", "2101"),
+	OMAP_TAG_VERSION_STR_CONFIG("nolo", "1.4.14"),
+	OMAP_TAG_VERSION_STR_CONFIG("boot-mode", "normal"),
+	{ }
+};
+
+static char *boot_reason_ptr;
+static char *hw_build_ptr;
+static char *nolo_version_ptr;
+static char *boot_mode_ptr;
+
+/*
+ * Routine: init_omap_tags
+ * Description: Initialize pointers to values in tag_omap
+ */
+static void init_omap_tags(void)
+{
+	char *component;
+	char *version;
+	int i = 0;
+	while (omap[i].hdr.tag) {
+		switch (omap[i].hdr.tag) {
+		case OMAP_TAG_BOOT_REASON:
+			boot_reason_ptr = omap[i].u.boot_reason.reason_str;
+			break;
+		case OMAP_TAG_VERSION_STR:
+			component = omap[i].u.version.component;
+			version = omap[i].u.version.version;
+			if (strcmp(component, "hw-build") == 0)
+				hw_build_ptr = version;
+			else if (strcmp(component, "nolo") == 0)
+				nolo_version_ptr = version;
+			else if (strcmp(component, "boot-mode") == 0)
+				boot_mode_ptr = version;
+			break;
+		default:
+			break;
+		}
+		i++;
+	}
+}
+
+static void reuse_omap_atags(struct tag_omap *t)
+{
+	char *component;
+	char *version;
+	while (t->hdr.tag) {
+		switch (t->hdr.tag) {
+		case OMAP_TAG_BOOT_REASON:
+			memset(boot_reason_ptr, 0, 12);
+			strcpy(boot_reason_ptr, t->u.boot_reason.reason_str);
+			break;
+		case OMAP_TAG_VERSION_STR:
+			component = t->u.version.component;
+			version = t->u.version.version;
+			if (strcmp(component, "hw-build") == 0) {
+				memset(hw_build_ptr, 0, 12);
+				strcpy(hw_build_ptr, version);
+			} else if (strcmp(component, "nolo") == 0) {
+				memset(nolo_version_ptr, 0, 12);
+				strcpy(nolo_version_ptr, version);
+			} else if (strcmp(component, "boot-mode") == 0) {
+				memset(boot_mode_ptr, 0, 12);
+				strcpy(boot_mode_ptr, version);
+			}
+			break;
+		default:
+			break;
+		}
+		t = tag_omap_next(t);
+	}
+}
+
+/*
+ * Routine: reuse_atags
+ * Description: Reuse atags from previous bootloader.
+ *              Reuse only only HW build, boot reason, boot mode and nolo
+ */
+static void reuse_atags(void)
+{
+	struct tag *t = (struct tag *)gd->bd->bi_boot_params;
+
+	/* First tag must be ATAG_CORE */
+	if (t->hdr.tag != ATAG_CORE)
+		return;
+
+	if (!boot_reason_ptr || !hw_build_ptr)
+		return;
+
+	/* Last tag must be ATAG_NONE */
+	while (t->hdr.tag != ATAG_NONE) {
+		switch (t->hdr.tag) {
+		case ATAG_REVISION:
+			memset(hw_build_ptr, 0, 12);
+			sprintf(hw_build_ptr, "%x", t->u.revision.rev);
+			break;
+		case ATAG_BOARD:
+			reuse_omap_atags((struct tag_omap *)&t->u);
+			break;
+		default:
+			break;
+		}
+		t = tag_next(t);
+	}
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	/* in SRAM or SDRAM, finish GPMC */
+	gpmc_init();
+	/* boot param addr */
+	gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
+	return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Return board revision.
+ */
+u32 get_board_rev(void)
+{
+	return simple_strtol(hw_build_ptr, NULL, 16);
+}
+
+/*
+ * Routine: setup_board_tags
+ * Description: Append board specific boot tags.
+ */
+void setup_board_tags(struct tag **in_params)
+{
+	int setup_console_atag;
+	char *setup_boot_reason_atag;
+	char *setup_boot_mode_atag;
+	char *str;
+	int i;
+	int size;
+	int total_size;
+	struct tag *params;
+	struct tag_omap *t;
+
+	params = (struct tag *)gd->bd->bi_boot_params;
+
+	params->u.core.flags = 0x0;
+	params->u.core.pagesize = 0x1000;
+	params->u.core.rootdev = 0x0;
+
+	/* append omap atag only if env setup_omap_atag is set to 1 */
+	str = getenv("setup_omap_atag");
+	if (!str || str[0] != '1')
+		return;
+
+	str = getenv("setup_console_atag");
+	if (str && str[0] == '1')
+		setup_console_atag = 1;
+	else
+		setup_console_atag = 0;
+
+	setup_boot_reason_atag = getenv("setup_boot_reason_atag");
+	setup_boot_mode_atag = getenv("setup_boot_mode_atag");
+
+	params = *in_params;
+	t = (struct tag_omap *)&params->u;
+	total_size = sizeof(struct tag_header);
+
+	for (i = 0; omap[i].hdr.tag; i++) {
+
+		/* skip serial console tag */
+		if (!setup_console_atag &&
+			omap[i].hdr.tag == OMAP_TAG_SERIAL_CONSOLE)
+			continue;
+
+		size = omap[i].hdr.size + sizeof(struct tag_omap_header);
+		memcpy(t, &omap[i], size);
+
+		/* set uart tag to 0 - disable serial console */
+		if (!setup_console_atag && omap[i].hdr.tag == OMAP_TAG_UART)
+			t->u.uart.enabled_uarts = 0;
+
+		/* change boot reason */
+		if (setup_boot_reason_atag &&
+			omap[i].hdr.tag == OMAP_TAG_BOOT_REASON) {
+			memset(t->u.boot_reason.reason_str, 0, 12);
+			strcpy(t->u.boot_reason.reason_str,
+				setup_boot_reason_atag);
+		}
+
+		/* change boot mode */
+		if (setup_boot_mode_atag &&
+			omap[i].hdr.tag == OMAP_TAG_VERSION_STR &&
+			strcmp(omap[i].u.version.component, "boot-mode") == 0) {
+			memset(t->u.version.version, 0, 12);
+			strcpy(t->u.version.version, setup_boot_mode_atag);
+		}
+
+		total_size += size;
+		t = tag_omap_next(t);
+
+	}
+
+	params->hdr.tag = ATAG_BOARD;
+	params->hdr.size = total_size >> 2;
+	params = tag_next(params);
+
+	*in_params = params;
+}
+
+/*
+ * Routine: video_hw_init
+ * Description: Set up the GraphicDevice depending on sys_boot.
+ */
+void *video_hw_init(void)
+{
+	/* fill in Graphic Device */
+	gdev.frameAdrs = 0x8f9c0000;
+	gdev.winSizeX = 800;
+	gdev.winSizeY = 480;
+	gdev.gdfBytesPP = 2;
+	gdev.gdfIndex = GDF_16BIT_565RGB;
+	memset((void *)gdev.frameAdrs, 0, 0xbb800);
+	return (void *) &gdev;
+}
+
+/*
+ * Routine: twl4030_regulator_set_mode
+ * Description: Set twl4030 regulator mode over i2c powerbus.
+ */
+static void twl4030_regulator_set_mode(u8 id, u8 mode)
+{
+	u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8,
+			TWL4030_PM_MASTER_PB_WORD_MSB);
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff,
+			TWL4030_PM_MASTER_PB_WORD_LSB);
+}
+
+static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
+{
+	u32 i, num_params = *parameters;
+	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
+
+	/*
+	 * copy the parameters to an un-cached area to avoid coherency
+	 * issues
+	 */
+	for (i = 0; i < num_params; i++) {
+		__raw_writel(*parameters, sram_scratch_space);
+		parameters++;
+		sram_scratch_space++;
+	}
+
+	/* Now make the PPA call */
+	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
+}
+
+/*
+ * Routine: omap3_update_aux_cr_secure_rx51
+ * Description: Modify the contents Auxiliary Control Register.
+ * Parameters:
+ *   set_bits - bits to set in ACR
+ *   clr_bits - bits to clear in ACR
+ */
+static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
+{
+	struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+	u32 acr;
+
+	/* Read ACR */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+	acr &= ~clear_bits;
+	acr |= set_bits;
+
+	emu_romcode_params.num_params = 2;
+	emu_romcode_params.param1 = acr;
+
+	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+				(u32 *)&emu_romcode_params);
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts.
+ */
+int misc_init_r(void)
+{
+	char buf[12];
+	u8 state;
+
+	/* reset lp5523 led */
+	i2c_set_bus_num(1);
+	state = 0xff;
+	i2c_write(0x32, 0x3d, 1, &state, 1);
+	i2c_set_bus_num(0);
+
+	/* initialize twl4030 power managment */
+	twl4030_power_init();
+
+	/* set VSIM to 1.8V */
+	twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+				TWL4030_PM_RECEIVER_VSIM_VSEL_18,
+				TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+				TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+	/* store I2C access state */
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state,
+			TWL4030_PM_MASTER_PB_CFG);
+
+	/* enable I2C access to powerbus (needed for twl4030 regulator) */
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02,
+			TWL4030_PM_MASTER_PB_CFG);
+
+	/* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
+	twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
+	twl4030_regulator_set_mode(RES_VSIM, RES_STATE_ACTIVE);
+	twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
+
+	/* restore I2C access state */
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state,
+			TWL4030_PM_MASTER_PB_CFG);
+
+	/* set env variable attkernaddr for relocated kernel */
+	sprintf(buf, "%#x", KERNEL_ADDRESS);
+	setenv("attkernaddr", buf);
+
+	/* initialize omap tags */
+	init_omap_tags();
+
+	/* reuse atags from previous bootloader */
+	reuse_atags();
+
+	dieid_num_r();
+	print_cpuinfo();
+
+	/*
+	 * Cortex-A8(r1p0..r1p2) errata 430973 workaround
+	 * Set IBE bit in Auxiliary Control Register
+	 */
+	omap3_update_aux_cr_secure_rx51(1 << 6, 0);
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_RX51();
+}
+
+static unsigned long int twl_wd_time; /* last time of watchdog reset */
+static unsigned long int twl_i2c_lock;
+
+/*
+ * Routine: hw_watchdog_reset
+ * Description: Reset timeout of twl4030 watchdog.
+ */
+void hw_watchdog_reset(void)
+{
+	u8 timeout = 0;
+
+	/* do not reset watchdog too often - max every 4s */
+	if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ)
+		return;
+
+	/* localy lock twl4030 i2c bus */
+	if (test_and_set_bit(0, &twl_i2c_lock))
+		return;
+
+	/* read actual watchdog timeout */
+	twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout,
+			TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+
+	/* timeout 0 means watchdog is disabled */
+	/* reset watchdog timeout to 31s (maximum) */
+	if (timeout != 0)
+		twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31,
+				TWL4030_PM_RECEIVER_WATCHDOG_CFG);
+
+	/* store last watchdog reset time */
+	twl_wd_time = get_timer(0);
+
+	/* localy unlock twl4030 i2c bus */
+	test_and_clear_bit(0, &twl_i2c_lock);
+}
+
+/*
+ * TWL4030 keypad handler for cfb_console
+ */
+
+static const char keymap[] = {
+	/* normal */
+	'q',  'o',  'p',  ',', '\b',    0,  'a',  's',
+	'w',  'd',  'f',  'g',  'h',  'j',  'k',  'l',
+	'e',  '.',    0,  '\r',   0,  'z',  'x',  'c',
+	'r',  'v',  'b',  'n',  'm',  ' ',  ' ',    0,
+	't',    0,    0,    0,    0,    0,    0,    0,
+	'y',    0,    0,    0,    0,    0,    0,    0,
+	'u',    0,    0,    0,    0,    0,    0,    0,
+	'i',    5,    6,    0,    0,    0,    0,    0,
+	/* fn */
+	'1',  '9',  '0',  '=', '\b',    0,  '*',  '+',
+	'2',  '#',  '-',  '_',  '(',  ')',  '&',  '!',
+	'3',  '?',  '^', '\r',    0,  156,  '$',  238,
+	'4',  '/', '\\',  '"', '\'',  '@',    0,  '<',
+	'5',  '|',  '>',    0,    0,    0,    0,    0,
+	'6',    0,    0,    0,    0,    0,    0,    0,
+	'7',    0,    0,    0,    0,    0,    0,    0,
+	'8',   16,   17,    0,    0,    0,    0,    0,
+};
+
+static u8 keys[8];
+static u8 old_keys[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+#define KEYBUF_SIZE 32
+static u8 keybuf[KEYBUF_SIZE];
+static u8 keybuf_head;
+static u8 keybuf_tail;
+
+/*
+ * Routine: rx51_kp_init
+ * Description: Initialize HW keyboard.
+ */
+int rx51_kp_init(void)
+{
+	int ret = 0;
+	u8 ctrl;
+	ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl,
+		TWL4030_KEYPAD_KEYP_CTRL_REG);
+
+	if (ret)
+		return ret;
+
+	/* turn on keyboard and use hardware scanning */
+	ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
+	ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
+	ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl,
+				TWL4030_KEYPAD_KEYP_CTRL_REG);
+	/* enable key event status */
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe,
+				TWL4030_KEYPAD_KEYP_IMR1);
+	/* enable interrupt generation on rising and falling */
+	/* this is a workaround for qemu twl4030 emulation */
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57,
+				TWL4030_KEYPAD_KEYP_EDR);
+	/* enable ISR clear on read */
+	ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05,
+				TWL4030_KEYPAD_KEYP_SIH_CTRL);
+	return 0;
+}
+
+static void rx51_kp_fill(u8 k, u8 mods)
+{
+	/* check if some cursor key without meta fn key was pressed */
+	if (!(mods & 2) && (k == 18 || k == 31 || k == 33 || k == 34)) {
+		keybuf[keybuf_tail++] = '\e';
+		keybuf_tail %= KEYBUF_SIZE;
+		keybuf[keybuf_tail++] = '[';
+		keybuf_tail %= KEYBUF_SIZE;
+		if (k == 18) /* up */
+			keybuf[keybuf_tail++] = 'A';
+		else if (k == 31) /* left */
+			keybuf[keybuf_tail++] = 'D';
+		else if (k == 33) /* down */
+			keybuf[keybuf_tail++] = 'B';
+		else if (k == 34) /* right */
+			keybuf[keybuf_tail++] = 'C';
+		keybuf_tail %= KEYBUF_SIZE;
+		return;
+	}
+
+	if (mods & 2) { /* fn meta key was pressed */
+		k = keymap[k+64];
+	} else {
+		k = keymap[k];
+		if (mods & 1) { /* ctrl key was pressed */
+			if (k >= 'a' && k <= 'z')
+				k -= 'a' - 1;
+		}
+		if (mods & 4) { /* shift key was pressed */
+			if (k >= 'a' && k <= 'z')
+				k += 'A' - 'a';
+			else if (k == '.')
+				k = ':';
+			else if (k == ',')
+				k = ';';
+		}
+	}
+	keybuf[keybuf_tail++] = k;
+	keybuf_tail %= KEYBUF_SIZE;
+}
+
+/*
+ * Routine: rx51_kp_tstc
+ * Description: Test if key was pressed (from buffer).
+ */
+int rx51_kp_tstc(void)
+{
+	u8 c, r, dk, i;
+	u8 intr;
+	u8 mods;
+
+	/* localy lock twl4030 i2c bus */
+	if (test_and_set_bit(0, &twl_i2c_lock))
+		return 0;
+
+	/* twl4030 remembers up to 2 events */
+	for (i = 0; i < 2; i++) {
+
+		/* check interrupt register for events */
+		twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr,
+				TWL4030_KEYPAD_KEYP_ISR1+(2*i));
+
+		/* no event */
+		if (!(intr&1))
+			continue;
+
+		/* read the key state */
+		i2c_read(TWL4030_CHIP_KEYPAD,
+			TWL4030_KEYPAD_FULL_CODE_7_0, 1, keys, 8);
+
+		/* cut out modifier keys from the keystate */
+		mods = keys[4] >> 4;
+		keys[4] &= 0x0f;
+
+		for (c = 0; c < 8; c++) {
+
+			/* get newly pressed keys only */
+			dk = ((keys[c] ^ old_keys[c])&keys[c]);
+			old_keys[c] = keys[c];
+
+			/* fill the keybuf */
+			for (r = 0; r < 8; r++) {
+				if (dk&1)
+					rx51_kp_fill((c*8)+r, mods);
+				dk = dk >> 1;
+			}
+
+		}
+
+	}
+
+	/* localy unlock twl4030 i2c bus */
+	test_and_clear_bit(0, &twl_i2c_lock);
+
+	return (KEYBUF_SIZE + keybuf_tail - keybuf_head)%KEYBUF_SIZE;
+}
+
+/*
+ * Routine: rx51_kp_getc
+ * Description: Get last pressed key (from buffer).
+ */
+int rx51_kp_getc(void)
+{
+	keybuf_head %= KEYBUF_SIZE;
+	while (!rx51_kp_tstc())
+		WATCHDOG_RESET();
+	return keybuf[keybuf_head++];
+}
+
+/*
+ * Routine: board_mmc_init
+ * Description: Initialize mmc devices.
+ */
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0, 0, 0);
+	omap_mmc_init(1, 0, 0);
+	return 0;
+}
diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h
new file mode 100644
index 0000000..e66e241
--- /dev/null
+++ b/board/nokia/rx51/rx51.h
@@ -0,0 +1,389 @@
+/*
+ * (C) Copyright 2012
+ * Ивайло Димитров <freemangordon@abv.bg>
+ *
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _RX51_H_
+#define _RX51_H_
+
+/* Needed for ROM SMC call */
+struct emu_hal_params_rx51 {
+	u32 num_params;
+	u32 param1;
+	u32 param2;
+	u32 param3;
+	u32 param4;
+};
+
+int print_cpuinfo(void);
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_RX51() \
+/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M1)) /*nDMA_REQ2*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*nDMA_REQ3*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS*/\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS*/\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+/* Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLK*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/* Expansion card */\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+/* Wireless LAN */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+/* Bluetooth */\
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144*/\
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
+/* Modem Interface */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/\
+	MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*SSI1_DAT*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*SSI1_FLAG*/\
+	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*SSI1_RDY*/\
+	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+/* Serial Interface */\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS*/\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX*/\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M4)) /*GPIO_168*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M4)) /*GPIO_183*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOM*/\
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+/* USB EHCI (port 2) */\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DA2*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DA7*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DA4*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DA5*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DA6*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | DIS | M3)) /*HSUSB2_DA3*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_NXT*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DA0*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3)) /*HSUSB2_DA1*/\
+/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*MMC1_WP*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MD*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DA0*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DA1*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DA2*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DA7*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DA4*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DA5*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DA6*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DA3*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26m*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespw*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswa*/\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9ni*/\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmare0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmare1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmare2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmare3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrs*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtc*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeu*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlere*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleac*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusfl*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusfl*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#define MUX_RX51_C() \
+	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTD | DIS | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IEN | PTD | DIS | M4)) /*GPIO_142*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN | PTD | DIS | M4)) /*GPIO_141*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/
+
+#endif
diff --git a/board/nokia/rx51/tag_omap.h b/board/nokia/rx51/tag_omap.h
new file mode 100644
index 0000000..60fa26f
--- /dev/null
+++ b/board/nokia/rx51/tag_omap.h
@@ -0,0 +1,311 @@
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2011
+ * marcel@mesa.nl, Mesa Consulting B.V.
+ *
+ * (C) Copyright 2004-2005
+ * Nokia Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*
+ *  Code copied from maemo kernel 2.6.28 file
+ *  arch/arm/plat-omap/include/mach/board.h
+ *
+ *  Information structures for board-specific data
+ *
+ *  Copyright (C) 2004	Nokia Corporation
+ *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+
+/* Different peripheral ids */
+#define OMAP_TAG_CLOCK		0x4f01
+#define OMAP_TAG_SERIAL_CONSOLE	0x4f03
+#define OMAP_TAG_USB		0x4f04
+#define OMAP_TAG_LCD		0x4f05
+#define OMAP_TAG_GPIO_SWITCH	0x4f06
+#define OMAP_TAG_UART		0x4f07
+#define OMAP_TAG_FBMEM		0x4f08
+#define OMAP_TAG_STI_CONSOLE	0x4f09
+#define OMAP_TAG_CAMERA_SENSOR	0x4f0a
+#define OMAP_TAG_PARTITION	0x4f0b
+#define OMAP_TAG_TEA5761	0x4f10
+#define OMAP_TAG_TMP105		0x4f11
+
+#define OMAP_TAG_BOOT_REASON	0x4f80
+#define OMAP_TAG_FLASH_PART_STR	0x4f81
+#define OMAP_TAG_VERSION_STR	0x4f82
+
+#define OMAP_TAG_NOKIA_BT	0x4e01
+#define OMAP_TAG_WLAN_CX3110X	0x4e02
+#define OMAP_TAG_CBUS		0x4e03
+#define OMAP_TAG_EM_ASIC_BB5	0x4e04
+
+
+struct omap_clock_config {
+	/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
+	u8 system_clock_type;
+};
+
+struct omap_serial_console_config {
+	u8 console_uart;
+	u32 console_speed;
+};
+
+struct omap_sti_console_config {
+	unsigned enable:1;
+	u8 channel;
+};
+
+struct omap_usb_config {
+	/* Configure drivers according to the connectors on your board:
+	 *  - "A" connector (rectagular)
+	 *	... for host/OHCI use, set "register_host".
+	 *  - "B" connector (squarish) or "Mini-B"
+	 *	... for device/gadget use, set "register_dev".
+	 *  - "Mini-AB" connector (very similar to Mini-B)
+	 *	... for OTG use as device OR host, initialize "otg"
+	 */
+	unsigned	register_host:1;
+	unsigned	register_dev:1;
+	u8		otg;	/* port number, 1-based:  usb1 == 2 */
+
+	u8		hmc_mode;
+
+	/* implicitly true if otg:  host supports remote wakeup? */
+	u8		rwc;
+
+	/* signaling pins used to talk to transceiver on usbN:
+	 *  0 == usbN unused
+	 *  2 == usb0-only, using internal transceiver
+	 *  3 == 3 wire bidirectional
+	 *  4 == 4 wire bidirectional
+	 *  6 == 6 wire unidirectional (or TLL)
+	 */
+	u8		pins[3];
+};
+
+struct omap_lcd_config {
+	char panel_name[16];
+	char ctrl_name[16];
+	s16  nreset_gpio;
+	u8   data_lines;
+};
+
+struct omap_fbmem_config {
+	u32 start;
+	u32 size;
+};
+
+struct omap_gpio_switch_config {
+	char name[12];
+	u16 gpio;
+	u8 flags:4;
+	u8 type:4;
+	unsigned int key_code:24; /* Linux key code */
+};
+
+struct omap_uart_config {
+	/* Bit field of UARTs present; bit 0 --> UART1 */
+	unsigned int enabled_uarts;
+};
+
+struct omap_tea5761_config {
+	u16 enable_gpio;
+};
+
+struct omap_partition_config {
+	char name[16];
+	unsigned int size;
+	unsigned int offset;
+	/* same as in include/linux/mtd/partitions.h */
+	unsigned int mask_flags;
+};
+
+struct omap_flash_part_str_config {
+	char part_table[0];
+};
+
+struct omap_boot_reason_config {
+	char reason_str[12];
+};
+
+struct omap_version_config {
+	char component[12];
+	char version[12];
+};
+
+/*
+ *  Code copied from maemo kernel 2.6.28 file
+ *  arch/arm/plat-omap/include/mach/board-nokia.h
+ *
+ *  Information structures for Nokia-specific board config data
+ *
+ *  Copyright (C) 2005  Nokia Corporation
+ */
+
+struct omap_bluetooth_config {
+	u8 chip_type;
+	u8 bt_wakeup_gpio;
+	u8 host_wakeup_gpio;
+	u8 reset_gpio;
+	u8 bt_uart;
+	u8 bd_addr[6];
+	u8 bt_sysclk;
+};
+
+struct omap_wlan_cx3110x_config {
+	u8 chip_type;
+	u8 reserverd;
+	s16 power_gpio;
+	s16 irq_gpio;
+	s16 spi_cs_gpio;
+};
+
+struct omap_cbus_config {
+	s16 clk_gpio;
+	s16 dat_gpio;
+	s16 sel_gpio;
+};
+
+struct omap_em_asic_bb5_config {
+	s16 retu_irq_gpio;
+	s16 tahvo_irq_gpio;
+};
+
+/*
+ *  omap_tag handling
+ *
+ *  processing omap tag structures
+ *
+ *  Copyright (C) 2011  marcel@mesa.nl, Mesa Consulting B.V.
+ *  Copyright (C) 2012  Pali Rohár <pali.rohar@gmail.com>
+ */
+
+/* TI OMAP specific information */
+#define ATAG_BOARD	0x414f4d50
+
+struct tag_omap_header {
+	u16 tag;
+	u16 size;
+};
+
+struct tag_omap {
+	struct tag_omap_header hdr;
+	union {
+		struct omap_clock_config clock;
+		struct omap_serial_console_config serial_console;
+		struct omap_sti_console_config sti_console;
+		struct omap_usb_config usb;
+		struct omap_lcd_config lcd;
+		struct omap_fbmem_config fbmem;
+		struct omap_gpio_switch_config gpio_switch;
+		struct omap_uart_config uart;
+		struct omap_tea5761_config tea5761;
+		struct omap_partition_config partition;
+		struct omap_flash_part_str_config flash_part_str;
+		struct omap_boot_reason_config boot_reason;
+		struct omap_version_config version;
+		struct omap_bluetooth_config bluetooth;
+		struct omap_wlan_cx3110x_config wlan_cx3110x;
+		struct omap_cbus_config cbus;
+		struct omap_em_asic_bb5_config em_asic_bb5;
+	} u;
+};
+
+#define tag_omap_next(t)	((struct tag_omap *)((u8 *)(t) + \
+				(t)->hdr.size + sizeof(struct tag_omap_header)))
+
+#define OMAP_TAG_HEADER_CONFIG(config, type) \
+	.hdr.tag = config, \
+	.hdr.size = sizeof(struct type)
+
+#define OMAP_TAG_UART_CONFIG(p1) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_UART, omap_uart_config), \
+		.u.uart.enabled_uarts = p1, \
+	}
+
+#define OMAP_TAG_SERIAL_CONSOLE_CONFIG(p1, p2) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_SERIAL_CONSOLE, \
+			omap_serial_console_config), \
+		.u.serial_console.console_uart = p1, \
+		.u.serial_console.console_speed = p2, \
+	}
+
+#define OMAP_TAG_LCD_CONFIG(p1, p2, p3, p4) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_LCD, omap_lcd_config), \
+		.u.lcd.panel_name = p1, \
+		.u.lcd.ctrl_name = p2, \
+		.u.lcd.nreset_gpio = p3, \
+		.u.lcd.data_lines = p4, \
+	}
+
+#define OMAP_TAG_GPIO_SWITCH_CONFIG(p1, p2, p3, p4, p5) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_GPIO_SWITCH, \
+			omap_gpio_switch_config), \
+		.u.gpio_switch.name = p1, \
+		.u.gpio_switch.gpio = p2, \
+		.u.gpio_switch.flags = p3, \
+		.u.gpio_switch.type = p4, \
+		.u.gpio_switch.key_code = p5, \
+	}
+
+#define OMAP_TAG_WLAN_CX3110X_CONFIG(p1, p2, p3, p4, p5) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_WLAN_CX3110X, \
+			omap_wlan_cx3110x_config), \
+		.u.wlan_cx3110x.chip_type = p1, \
+		.u.wlan_cx3110x.reserverd = p2, \
+		.u.wlan_cx3110x.power_gpio = p3, \
+		.u.wlan_cx3110x.irq_gpio = p4, \
+		.u.wlan_cx3110x.spi_cs_gpio = p5, \
+	}
+
+#define OMAP_TAG_PARTITION_CONFIG(p1, p2, p3, p4) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_PARTITION, \
+			omap_partition_config), \
+		.u.partition.name = p1, \
+		.u.partition.size = p2, \
+		.u.partition.offset = p3, \
+		.u.partition.mask_flags = p4, \
+	}
+
+#define OMAP_TAG_BOOT_REASON_CONFIG(p1) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_BOOT_REASON, \
+			omap_boot_reason_config), \
+		.u.boot_reason.reason_str = p1, \
+	}
+
+#define OMAP_TAG_VERSION_STR_CONFIG(p1, p2) \
+	{ \
+		OMAP_TAG_HEADER_CONFIG(OMAP_TAG_VERSION_STR, \
+			omap_version_config), \
+		.u.version.component = p1, \
+		.u.version.version = p2, \
+	}
diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile
index a93d458..f6f419e 100644
--- a/board/nvidia/common/Makefile
+++ b/board/nvidia/common/Makefile
@@ -25,9 +25,7 @@ endif
 
 LIB	= $(obj)lib$(VENDOR).o
 
-COBJS-y += board.o
-COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o
-COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
+include common.mk
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk
new file mode 100644
index 0000000..bd6202c
--- /dev/null
+++ b/board/nvidia/common/common.mk
@@ -0,0 +1,4 @@
+# common options for all tegra boards
+COBJS-y	+= ../../nvidia/common/board.o
+COBJS-$(CONFIG_SPI_UART_SWITCH) += ../../nvidia/common/uart-spi-switch.o
+COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
index ca5facb..5645a8d 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -8,6 +8,7 @@
 
 	aliases {
 		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5004000";
 	};
 
 	memory {
@@ -52,7 +53,7 @@
 	};
 
 	usb@c5004000 {
-		status = "disabled";
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
 	};
 
 	nand-controller@70008000 {
diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts
index 38599bd..f830cf3 100644
--- a/board/nvidia/dts/tegra20-whistler.dts
+++ b/board/nvidia/dts/tegra20-whistler.dts
@@ -9,7 +9,6 @@
 	aliases {
 		i2c0 = "/i2c@7000d000";
 		usb0 = "/usb@c5008000";
-		usb1 = "/usb@c5000000";
 	};
 
 	memory {
@@ -61,6 +60,10 @@
 		};
 	};
 
+	usb@c5000000 {
+		status = "disabled";
+	};
+
 	usb@c5004000 {
 		status = "disabled";
 	};
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index 32ed9bb..c7590ac 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -75,3 +75,12 @@ int board_mmc_init(bd_t *bd)
 	return 0;
 }
 #endif
+
+void pin_mux_usb(void)
+{
+	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+	pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PINGRP_CDEV2);
+	/* USB2 PHY reset GPIO */
+	pinmux_tristate_disable(PINGRP_UAC);
+}
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 4e8a183..c412c07 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -26,6 +26,7 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
@@ -34,24 +35,15 @@
 #endif
 
 /* TODO: Remove this code when the SPI switch is working */
-#ifndef CONFIG_SPI_UART_SWITCH
-/*
- * Routine: gpio_config_uart_seaboard
- * Description: Force GPIO_PI3 low on Seaboard so UART4 works.
- */
-static void gpio_config_uart_seaboard(void)
+#if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
+void gpio_early_init_uart(void)
 {
 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
+#ifndef CONFIG_SPL_BUILD
 	gpio_request(GPIO_PI3, NULL);
+#endif
 	gpio_direction_output(GPIO_PI3, 0);
 }
-
-void gpio_early_init_uart(void)
-{
-	if (machine_is_ventana())
-		return;
-	gpio_config_uart_seaboard();
-}
 #endif
 
 #ifdef CONFIG_TEGRA_MMC
diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds
index fd4e8a5..c8d3894 100644
--- a/board/nx823/u-boot.lds
+++ b/board/nx823/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug
index c771102..92796e6 100644
--- a/board/nx823/u-boot.lds.debug
+++ b/board/nx823/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/board/openrisc/openrisc-generic/u-boot.lds
index 1aed197..4cffacb 100644
--- a/board/openrisc/openrisc-generic/u-boot.lds
+++ b/board/openrisc/openrisc-generic/u-boot.lds
@@ -26,9 +26,11 @@ SECTIONS
 		_endtext = .;
 	}  > ram
 
-	 __u_boot_cmd_start = .;
-	 .u_boot_cmd : { *(.u_boot_cmd) } > ram
-	 __u_boot_cmd_end = .;
+
+	 . = ALIGN(4);
+	 .u_boot_list : {
+	#include <u-boot.lst>
+	 }
 
 	.rodata : {
 		*(.rodata);
diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c
index b23eec8..590ca41 100644
--- a/board/palmtc/palmtc.c
+++ b/board/palmtc/palmtc.c
@@ -24,6 +24,7 @@
 #include <serial.h>
 #include <asm/io.h>
 #include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,6 +52,14 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
+
 int dram_init(void)
 {
 	pxa2xx_dram_init();
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
index bd0dee1..07ddd36 100644
--- a/board/pb1x00/u-boot.lds
+++ b/board/pb1x00/u-boot.lds
@@ -54,10 +54,9 @@ SECTIONS
 
 	.sdata  : { *(.sdata*) }
 
-	.u_boot_cmd : {
-	  __u_boot_cmd_start = .;
-	  *(.u_boot_cmd)
-	  __u_boot_cmd_end = .;
+	. = ALIGN(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
 
 	uboot_end_data = .;
diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c
index 5f89d9b..de61ca0 100644
--- a/board/pcippc2/fpga_serial.c
+++ b/board/pcippc2/fpga_serial.c
@@ -73,13 +73,6 @@ void fpga_serial_putc (char c)
 	}
 }
 
-void fpga_serial_puts (const char *s)
-{
-	while (*s) {
-		fpga_serial_print (*s++);
-	}
-}
-
 int fpga_serial_getc (void)
 {
 	while ((in8 (UART (LSR)) & 0x01) == 0);
diff --git a/board/pcippc2/fpga_serial.h b/board/pcippc2/fpga_serial.h
index 5275014..106fbf7 100644
--- a/board/pcippc2/fpga_serial.h
+++ b/board/pcippc2/fpga_serial.h
@@ -26,7 +26,6 @@
 
 extern void	fpga_serial_init	(int);
 extern void	fpga_serial_putc	(char);
-extern void	fpga_serial_puts	(const char *);
 extern int	fpga_serial_getc	(void);
 extern int	fpga_serial_tstc	(void);
 extern void	fpga_serial_setbrg	(void);
diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c
index 4a91458..5e6fc58 100644
--- a/board/pcippc2/pcippc2.c
+++ b/board/pcippc2/pcippc2.c
@@ -29,6 +29,7 @@
 #include <watchdog.h>
 #include <pci.h>
 #include <netdev.h>
+#include <serial.h>
 
 #include "hardware.h"
 #include "pcippc2.h"
@@ -129,7 +130,7 @@ int misc_init_r (void)
 	fpga_serial_init (sconsole_get_baudrate ());
 
 	sconsole_putc   = fpga_serial_putc;
-	sconsole_puts   = fpga_serial_puts;
+	sconsole_puts   = default_serial_puts;
 	sconsole_getc   = fpga_serial_getc;
 	sconsole_tstc   = fpga_serial_tstc;
 	sconsole_setbrg = fpga_serial_setbrg;
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 746a54c..f8345dd 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -32,6 +32,7 @@
 #include <sha1.h>
 #include <asm/io.h>
 #include <net.h>
+#include <ata.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -672,7 +673,6 @@ U_BOOT_CMD(
  * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
  * These values are shifted
  */
-extern ulong *ide_bus_offset;
 void inline ide_outb(int dev, int port, unsigned char val)
 {
 	debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
@@ -714,3 +714,58 @@ void ide_set_reset (int idereset)
 	udelay (10000);
 }
 #endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+
+/* this is motly the same as it should, causing a little code duplication */
+#if defined(CONFIG_CMD_IDE)
+#define EIEIO		__asm__ volatile ("eieio")
+
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	volatile ushort *pbuf =
+		(ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	ushort *dbuf = (ushort *) sect_buf;
+
+	debug("in input swap data base for read is %lx\n",
+		(unsigned long) pbuf);
+
+	while (words--) {
+		*dbuf++ = *pbuf;
+		*dbuf++ = *pbuf;
+	}
+}
+
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *) sect_buf;
+	while (words--) {
+		EIEIO;
+		*pbuf = ld_le16(dbuf++);
+		EIEIO;
+		*pbuf = ld_le16(dbuf++);
+	}
+}
+
+void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+	ushort *dbuf;
+	volatile ushort *pbuf;
+
+	pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+	dbuf = (ushort *) sect_buf;
+
+	debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+
+	while (words--) {
+		EIEIO;
+		*dbuf++ = ld_le16(pbuf);
+		EIEIO;
+		*dbuf++ = ld_le16(pbuf);
+	}
+}
+
+#endif
diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c
index 2f4d294..3536933 100644
--- a/board/prodrive/p3mx/serial.c
+++ b/board/prodrive/p3mx/serial.c
@@ -75,21 +75,13 @@ static void p3mx_serial_setbrg(void)
 	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
 }
 
-
-static void p3mx_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
 static struct serial_device p3mx_serial_drv = {
 	.name	= "p3mx_serial",
 	.start	= p3mx_serial_init,
 	.stop	= NULL,
 	.setbrg	= p3mx_serial_setbrg,
 	.putc	= p3mx_serial_putc,
-	.puts	= p3mx_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= p3mx_serial_getc,
 	.tstc	= p3mx_serial_tstc,
 };
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index 877e8d9..9931efd 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -35,6 +35,7 @@
 #include <command.h>
 #include <asm/io.h>
 #include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -77,6 +78,14 @@ int board_init (void)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
+
 int board_late_init(void)
 {
 	setenv("stdout", "serial");
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
deleted file mode 100644
index 27cd34a..0000000
--- a/board/qemu-mips/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc00000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..cb2356f 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
 /*
 OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
 */
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
+#else
 OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+#endif
 OUTPUT_ARCH(mips)
 ENTRY(_start)
 SECTIONS
@@ -55,15 +59,17 @@ SECTIONS
 	. = ALIGN(4);
 	.sdata  : { *(.sdata*) }
 
-	. = .;
-	.u_boot_cmd : {
-	__u_boot_cmd_start = .;
-	*(.u_boot_cmd)
-	__u_boot_cmd_end = .;
+	. = ALIGN(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
 
 	uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+	num_got_entries = (__got_end - __got_start) >> 3;
+#else
 	num_got_entries = (__got_end - __got_start) >> 2;
+#endif
 
 	. = ALIGN(4);
 	.sbss  : { *(.sbss*) }
diff --git a/board/qi/qi_lb60/u-boot.lds b/board/qi/qi_lb60/u-boot.lds
index 7317652..b3cb869 100644
--- a/board/qi/qi_lb60/u-boot.lds
+++ b/board/qi/qi_lb60/u-boot.lds
@@ -47,9 +47,11 @@ SECTIONS
 
 	.sdata  : { *(.sdata*) }
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	uboot_end_data = .;
 	num_got_entries = (__got_end - __got_start) >> 2;
diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/quantum/u-boot.lds
+++ b/board/quantum/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds
index 2fa085a..3ef0d9e 100644
--- a/board/r360mpi/u-boot.lds
+++ b/board/r360mpi/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds
index d943fb6..a86b568 100644
--- a/board/rbc823/u-boot.lds
+++ b/board/rbc823/u-boot.lds
@@ -77,9 +77,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds
index 38ebe88..cf406ce 100644
--- a/board/renesas/sh7757lcr/u-boot.lds
+++ b/board/renesas/sh7757lcr/u-boot.lds
@@ -77,13 +77,10 @@ SECTIONS
 	}
 	PROVIDE (_egot = .);
 
-	PROVIDE (__u_boot_cmd_start = .);
-	.u_boot_cmd :
-	{
-		*(.u_boot_cmd)
-		. = ALIGN(4);
+
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
-	PROVIDE (__u_boot_cmd_end = .);
 
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds
index a729c52..ff95029 100644
--- a/board/rsdproto/u-boot.lds
+++ b/board/rsdproto/u-boot.lds
@@ -97,9 +97,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index 9283201..9daa0da 100644
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -158,7 +158,22 @@ system_clock_init:
 	ldr	r2, =CLK_SRC_PERIL0_OFFSET
 	str	r1, [r0, r2]
 
-	/* FIMD0 */
+	/* CAM , FIMC 0-3 */
+	ldr	r1, =CLK_SRC_CAM_VAL
+	ldr	r2, =CLK_SRC_CAM_OFFSET
+	str	r1, [r0, r2]
+
+	/* MFC */
+	ldr	r1, =CLK_SRC_MFC_VAL
+	ldr	r2, =CLK_SRC_MFC_OFFSET
+	str	r1, [r0, r2]
+
+	/* G3D */
+	ldr	r1, =CLK_SRC_G3D_VAL
+	ldr	r2, =CLK_SRC_G3D_OFFSET
+	str	r1, [r0, r2]
+
+	/* LCD0 */
 	ldr	r1, =CLK_SRC_LCD0_VAL
 	ldr	r2, =CLK_SRC_LCD0_OFFSET
 	str	r1, [r0, r2]
@@ -223,6 +238,26 @@ system_clock_init:
 	ldr	r2, =CLK_DIV_PERIL0_OFFSET
 	str	r1, [r0, r2]
 
+	/* CAM, FIMC 0-3: CAM Clock Divisors */
+	ldr	r1, =CLK_DIV_CAM_VAL
+	ldr	r2, =CLK_DIV_CAM_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_MFC: MFC Clock Divisors */
+	ldr	r1, =CLK_DIV_MFC_VAL
+	ldr	r2, =CLK_DIV_MFC_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_G3D: G3D Clock Divisors */
+	ldr	r1, =CLK_DIV_G3D_VAL
+	ldr	r2, =CLK_DIV_G3D_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_LCD0: LCD0 Clock Divisors */
+	ldr	r1, =CLK_DIV_LCD0_VAL
+	ldr	r2, =CLK_DIV_LCD0_OFFSET
+	str	r1, [r0, r2]
+
 	/* Set PLL locktime */
 	ldr	r1, =PLL_LOCKTIME
 	ldr	r2, =APLL_LOCK_OFFSET
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index 94cccca..930b948 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -53,7 +53,18 @@
 #define CLK_DIV_FSYS2_OFFSET	0xC548
 #define CLK_DIV_FSYS3_OFFSET	0xC54C
 
+#define CLK_SRC_CAM_OFFSET	0xC220
+#define CLK_SRC_TV_OFFSET	0xC224
+#define CLK_SRC_MFC_OFFSET	0xC228
+#define CLK_SRC_G3D_OFFSET	0xC22C
+#define CLK_SRC_LCD0_OFFSET	0xC234
 #define CLK_SRC_PERIL0_OFFSET	0xC250
+
+#define CLK_DIV_CAM_OFFSET	0xC520
+#define CLK_DIV_TV_OFFSET	0xC524
+#define CLK_DIV_MFC_OFFSET	0xC528
+#define CLK_DIV_G3D_OFFSET	0xC52C
+#define CLK_DIV_LCD0_OFFSET	0xC534
 #define CLK_DIV_PERIL0_OFFSET	0xC550
 
 #define CLK_SRC_LCD0_OFFSET	0xC234
@@ -353,6 +364,65 @@
 				| (UART1_RATIO << 4) \
 				| (UART0_RATIO << 0))
 
+/* Clock Source CAM/FIMC */
+/* CLK_SRC_CAM */
+#define CAM0_SEL_XUSBXTI	1
+#define CAM1_SEL_XUSBXTI	1
+#define CSIS0_SEL_XUSBXTI	1
+#define CSIS1_SEL_XUSBXTI	1
+
+#define FIMC_SEL_SCLKMPLL	6
+#define FIMC0_LCLK_SEL		FIMC_SEL_SCLKMPLL
+#define FIMC1_LCLK_SEL		FIMC_SEL_SCLKMPLL
+#define FIMC2_LCLK_SEL		FIMC_SEL_SCLKMPLL
+#define FIMC3_LCLK_SEL		FIMC_SEL_SCLKMPLL
+
+#define CLK_SRC_CAM_VAL		((CSIS1_SEL_XUSBXTI << 28) \
+				| (CSIS0_SEL_XUSBXTI << 24) \
+				| (CAM1_SEL_XUSBXTI << 20) \
+				| (CAM0_SEL_XUSBXTI << 16) \
+				| (FIMC3_LCLK_SEL << 12) \
+				| (FIMC2_LCLK_SEL << 8) \
+				| (FIMC1_LCLK_SEL << 4) \
+				| (FIMC0_LCLK_SEL << 0))
+
+/* SCLK CAM */
+/* CLK_DIV_CAM */
+#define FIMC0_LCLK_RATIO	4
+#define FIMC1_LCLK_RATIO	4
+#define FIMC2_LCLK_RATIO	4
+#define FIMC3_LCLK_RATIO	4
+#define CLK_DIV_CAM_VAL		((FIMC3_LCLK_RATIO << 12) \
+				| (FIMC2_LCLK_RATIO << 8) \
+				| (FIMC1_LCLK_RATIO << 4) \
+				| (FIMC0_LCLK_RATIO << 0))
+
+/* SCLK MFC */
+/* CLK_SRC_MFC */
+#define MFC_SEL_MPLL		0
+#define MOUTMFC_0		0
+#define MFC_SEL			MOUTMFC_0
+#define MFC_0_SEL		MFC_SEL_MPLL
+#define CLK_SRC_MFC_VAL		((MFC_SEL << 8) | (MFC_0_SEL))
+
+
+/* CLK_DIV_MFC */
+#define MFC_RATIO		3
+#define CLK_DIV_MFC_VAL		(MFC_RATIO)
+
+/* SCLK G3D */
+/* CLK_SRC_G3D */
+#define G3D_SEL_MPLL		0
+#define MOUTG3D_0		0
+#define G3D_SEL			MOUTG3D_0
+#define G3D_0_SEL		G3D_SEL_MPLL
+#define CLK_SRC_G3D_VAL		((G3D_SEL << 8) | (G3D_0_SEL))
+
+/* CLK_DIV_G3D */
+#define G3D_RATIO		1
+#define CLK_DIV_G3D_VAL		(G3D_RATIO)
+
+/* SCLK LCD0 */
 /* CLK_SRC_LCD0 */
 #define FIMD_SEL_SCLKMPLL	6
 #define MDNIE0_SEL_XUSBXTI	1
@@ -363,6 +433,10 @@
 				| (MDNIE0_SEL_XUSBXTI << 4) \
 				| (FIMD_SEL_SCLKMPLL << 0))
 
+/* CLK_DIV_LCD0 */
+#define FIMD0_RATIO		4
+#define CLK_DIV_LCD0_VAL	(FIMD0_RATIO)
+
 /* Required period to generate a stable clock output */
 /* PLL_LOCK_TIME */
 #define PLL_LOCKTIME		0x1C20
diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds
index d78dd77..951d8ce 100644
--- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds
+++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds
@@ -48,6 +48,11 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 	. = ALIGN(4);
 
+	.u_boot_list : {
+		#include <u-boot.lst>
+	} >.sram
+	. = ALIGN(4);
+
 	/* Align .machine_param on 256 byte boundary for easier searching */
 	.machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
 	. = ALIGN(4);
diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds
index f162815..fbb442a 100644
--- a/board/samsung/smdk6400/u-boot-nand.lds
+++ b/board/samsung/smdk6400/u-boot-nand.lds
@@ -47,11 +47,13 @@ SECTIONS
 	. = ALIGN(4);
 	.got : { *(.got) }
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
 
-	. = ALIGN(4);
+	. = align(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
+
+	. = align(4);
 	.mmudata : { *(.mmudata) }
 
 	. = ALIGN(4);
diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug
index 31746e3..7a0757f 100644
--- a/board/sandburst/karef/u-boot.lds.debug
+++ b/board/sandburst/karef/u-boot.lds.debug
@@ -115,9 +115,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug
index 4922bd2..07bd6fe 100644
--- a/board/sandburst/metrobox/u-boot.lds.debug
+++ b/board/sandburst/metrobox/u-boot.lds.debug
@@ -115,9 +115,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds
index e382fd1..ae3afa1 100644
--- a/board/sandpoint/u-boot.lds
+++ b/board/sandpoint/u-boot.lds
@@ -68,9 +68,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/sbc8560/README b/board/sbc8560/README
deleted file mode 100644
index c4b6422..0000000
--- a/board/sbc8560/README
+++ /dev/null
@@ -1,57 +0,0 @@
-The port was tested on Wind River System Sbc8560 board
-<www.windriver.com>. U-Boot was installed on the flash memory of the
-CPU card (no the SODIMM).
-
-NOTE: Please configure uboot compile to the proper PCI frequency and
-setup the appropriate DIP switch settings.
-
-SBC8560 board:
-
-Make sure boards switches are set to their appropriate conditions.
-Refer to the Engineering Reference Guide ERG-00300-002. Of particular
-importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which
-select the on-board FLASH device (Intel 28F128Jx); 2) The settings
-for the Clock SW9 (33 MHz or 66 MHz).
-
-	Note:	SW9 Settings: 66 MHz
-		4:1 ratio CCB clocks:SYSCLK
-		3:1 ration e500 Core:CCB
-		pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on
-	Note:	SW9 Settings: 33 MHz
-		8:1 ratio CCB clocks:SYSCLK
-		3:1 ration e500 Core:CCB
-		pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on
-
-
-Flashing the FLASH device with the "Wind River ICE":
-
-1) Properly connect and configure the Wind River ICE to the target
-   JTAG port. This includes running the SBC8560 register script. Make
-   sure target memory can be read and written.
-
-2) Build the u-boot image:
-	make distclean
-	make SBC8560_66_config or SBC8560_33_config
-	make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all
-
-   Note: reference is made to the ELDK3.0 compiler. Further, it seems
-	 the ppc_8xx compiler is required for the 85xx (no 85xx
-	 designated compiler in ELDK3.0)
-
-3) Convert the uboot (.elf) file to a uboot.bin file (using
-   visionClick converter). The bin file should be converted from
-   fffc0000 to ffffffff
-
-4) Setup the Flash Utility (tools menu) for:
-
-   Do a "dc clr" [visionClick] to load the default register settings
-   Determine the clock speed of the PCI bus and set SW9 accordingly
-	Note: the speed of the PCI bus defaults to the slowest PCI card
-   PlayBack the "default" register file for the SBC8560
-   Select the uboot.bin file with zero bias
-   Select the initialize Target prior to programming
-   Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm
-   Select the erase base address from FFFC0000 to FFFFFFFF
-   Select the start address from 0 with size of 4000
-
-5) Erase and Program
diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c
deleted file mode 100644
index e9babc6..0000000
--- a/board/sbc8560/ddr.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 0;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c
deleted file mode 100644
index 4e6baed..0000000
--- a/board/sbc8560/law.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/* LAW(Local Access Window) configuration:
- * 0000_0000-0800_0000: DDR(512M) -or- larger
- * c000_0000-cfff_ffff: PCI(256M)
- * d000_0000-dfff_ffff: RapidIO(256M)
- * e000_0000-ffff_ffff: localbus(512M)
- *   e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
- *   e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
- *   e800_0000-efff_ffff: LBC 128M, nothing here
- *   f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
- *   f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
- *   f800_0000-fdff_ffff: LBC 64M, nothing here
- *   fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
- *   fd00_0000-fdff_ffff: LBC 16M, nothing here
- *   fe00_0000-feff_ffff: LBC 16M, nothing here
- *   ff00_0000-ff6f_ffff: LBC 7M, nothing here
- *   ff70_0000-ff7f_ffff: CCSRBAR 1M
- *   ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
- * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
- *       Window.
- * Note: If flash is 8M at default position(last 8M),no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-#endif
-	SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
deleted file mode 100644
index 98bc7df..0000000
--- a/board/sbc8560/sbc8560.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8560 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
-	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
-	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
-	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
-	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
-	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
-	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
-	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
-	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
-	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
-	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
-	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
-	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
-	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
-	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
-	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
-	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
-	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
-	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
-    },
-
-    /* Port D */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
-	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
-	/* PD27 */ {   1,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
-	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-int board_early_init_f (void)
-{
-#if defined(CONFIG_PCI)
-    volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-
-    pci->peer &= 0xfffffffdf; /* disable master abort */
-#endif
-	return 0;
-}
-
-void reset_phy (void)
-{
-#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
-	volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
-#endif
-	/* reset Giga bit Ethernet port if needed here */
-
-	/* reset the CPM FEC port */
-#if (CONFIG_ETHER_INDEX == 2)
-	bcsr[0] &= ~0x20;
-	udelay(2);
-	bcsr[0] |= 0x20;
-	udelay(1000);
-#elif (CONFIG_ETHER_INDEX == 3)
-	bcsr[0] &= ~0x10;
-	udelay(2);
-	bcsr[0] |= 0x10;
-	udelay(1000);
-#endif
-#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
-	/* reset PHY */
-	miiphy_reset("FCC1", 0x0);
-
-	/* change PHY address to 0x02 */
-	bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
-
-	bb_miiphy_write(NULL, 0x02, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_MII */
-}
-
-int checkboard (void)
-{
-	sys_info_t sysinfo;
-	char buf[32];
-
-	get_sys_info (&sysinfo);
-
-#ifdef CONFIG_SBC8560
-	printf ("Board: Wind River SBC8560 Board\n");
-#else
-	printf ("Board: Wind River SBC8540 Board\n");
-#endif
-	printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
-	printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
-	printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
-	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
-		|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
-		printf ("\tLBC: %s MHz\n",
-			strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
-	} else {
-		printf("\tLBC: unknown\n");
-	}
-	printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
-	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
-	return (0);
-}
-
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
-	uint *p;
-
-	printf("SDRAM test phase 1:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf("SDRAM test phase 2:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf("SDRAM test passed.\n");
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
-
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000
-
-  #ifndef CONFIG_SYS_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
-#if (CONFIG_SYS_SDRAM_SIZE == 512)
-	ddr->cs0_bnds		= 0x0000000f;
-#else
-	ddr->cs0_bnds		= 0x00000007;
-#endif
-	ddr->cs1_bnds		= 0x0010001f;
-	ddr->cs2_bnds		= 0x00000000;
-	ddr->cs3_bnds		= 0x00000000;
-	ddr->cs0_config		= 0x80000102;
-	ddr->cs1_config		= 0x80000102;
-	ddr->cs2_config		= 0x00000000;
-	ddr->cs3_config		= 0x00000000;
-	ddr->timing_cfg_1	= 0x37334321;
-	ddr->timing_cfg_2	= 0x00000800;
-	ddr->sdram_cfg		= 0x42000000;
-	ddr->sdram_mode		= 0x00000022;
-	ddr->sdram_interval	= 0x05200100;
-	ddr->err_sbe		= 0x00ff0000;
-    #if defined (CONFIG_DDR_ECC)
-	ddr->err_disable = 0x0000000D;
-    #endif
-	asm("sync;isync;msync");
-	udelay(500);
-    #if defined (CONFIG_DDR_ECC)
-	/* Enable ECC checking */
-	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-    #else
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-    #endif
-	asm("sync; isync; msync");
-	udelay(500);
-  #endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif	/* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
-	int node;
-#ifdef CONFIG_PCI
-	const char *path;
-#endif
-
-	ft_cpu_setup(blob, bd);
-
-	node = fdt_path_offset(blob, "/aliases");
-	if (node >= 0) {
-#ifdef CONFIG_PCI
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			tmp[1] = hose.last_busno - hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-#endif
-	}
-}
-#endif
diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c
deleted file mode 100644
index fe0ac76..0000000
--- a/board/sbc8560/tlb.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-/* TLB for CCSRBAR (IMMR) */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_1M, 1),
-
-/* TLB for Local Bus stuff, just map the whole 512M */
-/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
-
-	SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 6, BOOKE_PAGESZ_16K, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_256M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c
deleted file mode 100644
index 7325a93..0000000
--- a/board/siemens/IAD210/IAD210.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * (C) Copyright 2001
- * Paul Geerinckx
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <net.h>
-#include "atm.h"
-#include <i2c.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-/* used PLD registers */
-#  define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
-#  define PLD_EXT_RES  (unsigned char *) (0x10000000 + 10)
-#  define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
-#  define PLD_EXT_LED  (unsigned char *) (0x10000000 + 12)
-#  define PLD_EXT_X21  (unsigned char *) (0x10000000 + 13)
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-const uint sdram_table[] = {
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47,	/* last */
-	_NOT_USED_,
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-	0xFFFAF834, 0xFFE5B435,	/* last */
-	_NOT_USED_,
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
-	0xF0AFFC00, 0xF0AAF800, 0xF1A5E447,	/* last */
-	_NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0xFE29B300, 0xF1A27304, 0xFFA5F747,	/* last */
-	_NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
-	0xF1AAF804, 0xFFA5F447,	/* last */
-	_NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Refresh  (Offset 30 in UPMA RAM)
-	 */
-	0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
-	0xFFAFFC07,		/* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * MRS sequence  (Offset 38 in UPMA RAM)
-	 */
-	0xFFAAB834, 0xFFA57434, 0xFFAFFC05,	/* last */
-	_NOT_USED_,
-	/*
-	 * Exception. (Offset 3c in UPMA RAM)
-	 */
-	0xFFAFFC04, 0xFFAFFC05,	/* last */
-	_NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile iop8xx_t *iop = &immap->im_ioport;
-	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
-	long int size;
-
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
-
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
-	 * preliminary addresses - these have to be modified after the
-	 * SDRAM size has been determined.
-	 */
-	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
-
-	/* perform SDRAM initializsation sequence */
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
-	udelay (1);
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM precharge */
-	udelay (1);
-	memctl->memc_mcr = 0x80004030;	/* SDRAM 16x autorefresh */
-	udelay (1);
-	memctl->memc_mcr = 0x80004138;	/* SDRAM upload parameters */
-	udelay (1);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (1000);
-
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 *
-	 */
-	size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM,
-			  SDRAM_MAX_SIZE);
-
-	udelay (1000);
-
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR;
-	udelay (1000);
-
-	/*
-	 * Final mapping
-	 */
-	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
-
-	udelay (10000);
-
-	/* prepare pin multiplexing for fast ethernet */
-
-	atmLoad ();
-	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */
-	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */
-
-
-	return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-			   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size (base, maxsize));
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	return (0);
-}
-
-void board_serial_init (void)
-{
-	;			/* nothing to do here */
-}
-
-void board_ether_init (void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile iop8xx_t *iop = &immap->im_ioport;
-	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
-
-	atmLoad ();
-	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */
-	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */
-}
-
-int board_early_init_f (void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile iop8xx_t *iop = &immap->im_ioport;
-
-	/* configure the LED timing output pins - port A pin 4 */
-	iop->iop_papar = 0x0800;
-	iop->iop_padir = 0x0800;
-
-	/* start timer 2 for the 4hz LED blink rate */
-	timers->cpmt_tmr2 = 0xff2c;	/* 4HZ for 64MHz */
-	timers->cpmt_trr2 = 0x000003d0;	/* clk/16 , prescale=256 */
-	timers->cpmt_tgcr = 0x00000810;	/* run timer 2 */
-
-	/* chip select for PLD access */
-	memctl->memc_br6 = 0x10000401;
-	memctl->memc_or6 = 0xFC000908;
-
-	/* PLD initial values ( set LEDs, remove reset on LXT) */
-
-	*PLD_GCR1_REG = 0x06;
-	*PLD_EXT_RES = 0xC0;
-	*PLD_EXT_FETH = 0x40;
-	*PLD_EXT_LED = 0xFF;
-	*PLD_EXT_X21 = 0x04;
-	return 0;
-}
-
-static void board_get_enetaddr(uchar *addr)
-{
-	int i;
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile cpm8xx_t *cpm = &immap->im_cpm;
-	unsigned int rccrtmp;
-
-	char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
-
-	for (i = 0; i < 6; i++)
-		addr[i] = default_mac_addr[i];
-
-	printf ("There is an error in the i2c driver .. /n");
-	printf ("You need to fix it first....../n");
-
-	rccrtmp = cpm->cp_rccr;
-	cpm->cp_rccr |= 0x0020;
-
-	i2c_reg_read (0xa0, 0);
-	printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
-		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
-		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
-		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
-
-	cpm->cp_rccr = rccrtmp;
-}
-
-int misc_init_r(void)
-{
-	uchar enetaddr[6];
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c
deleted file mode 100644
index 40aad0a..0000000
--- a/board/siemens/IAD210/atm.c
+++ /dev/null
@@ -1,652 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-
-#include "atm.h"
-#include <linux/stddef.h>
-
-#define SYNC __asm__("sync")
-#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
-
-#define FALSE  1
-#define TRUE   0
-#define OK     0
-#define ERROR -1
-
-struct atm_connection_t g_conn[NUM_CONNECTIONS] =
-{
-  { NULL, 10, NULL, 10,  NULL, NULL, NULL, NULL }, /* OAM  */
-};
-
-struct atm_driver_t g_atm =
-{
-  FALSE,   /* loaded */
-  FALSE,   /* started */
-  NULL,    /* csram */
-  0,       /* csram_size */
-  NULL,    /* am_top */
-  NULL,    /* ap_top */
-  NULL,    /* int_reload_ptr */
-  NULL,    /* int_serv_ptr */
-  NULL,    /* rbd_base_ptr */
-  NULL,    /* tbd_base_ptr */
-  0        /* linerate */
-};
-
-char csram[1024]; /* more than enough for doing nothing*/
-
-int    atmLoad(void);
-void   atmUnload(void);
-int    atmMemInit(void);
-void   atmIntInit(void);
-void   atmApcInit(void);
-void   atmAmtInit(void);
-void   atmCpmInit(void);
-void   atmUtpInit(void);
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmLoad
- *
- * DESCRIPTION: Basic ATM initialization.
- *
- * PARAMETERS: none
- *
- * RETURNS: OK or ERROR
- *
- ****************************************************************************/
-int atmLoad()
-{
-  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
-  volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
-  volatile iop8xx_t      *iop    = &immap->im_ioport;
-
-  timers->cpmt_tgcr &=  0x0FFF; SYNC;             /* Disable Timer 4 */
-  immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
-  iop->iop_pdpar &= 0x3FFF; SYNC;                 /* Disable SAR and UTOPIA */
-
-  if ( atmMemInit() != OK ) return ERROR;
-
-  atmIntInit();
-  atmApcInit();
-  atmAmtInit();
-  atmCpmInit();
-  atmUtpInit();
-
-  g_atm.loaded = TRUE;
-
-  return OK;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmUnload
- *
- * DESCRIPTION: Disables ATM and UTOPIA.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmUnload()
-{
-  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
-  volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
-  volatile iop8xx_t      *iop    = &immap->im_ioport;
-
-  timers->cpmt_tgcr &=  0x0FFF; SYNC;             /* Disable Timer 4 */
-  immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC;  /* Disable SCC4 */
-  iop->iop_pdpar &= 0x3FFF; SYNC;                 /* Disable SAR and UTOPIA */
-  g_atm.loaded = FALSE;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmMemInit
- *
- * DESCRIPTION:
- *
- * The ATM driver uses the following resources:
- *
- * A. Memory in DPRAM to hold
- *
- *     1/ CT          = Connection Table ( RCT & TCT )
- *     2/ TCTE        = Transmit Connection Table Extension
- *     3/ MPHYPT      = Multi-PHY Pointing Table
- *     4/ APCP        = APC Parameter Table
- *     5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
- *     6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
- *     7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
- *     8/ TQ          = Transmit Queue
- *     9/ AM          = Address Matching Table
- *    10/ AP          = Address Pointing Table
- *
- * B. Memory in cache safe RAM to hold
- *
- *     1/ INT         = Interrupt Queue
- *     2/ RBD         = Receive Buffer Descriptors
- *     3/ TBD         = Transmit Buffer Descriptors
- *
- * This function
- * 1. clears the ATM DPRAM area,
- * 2. Allocates and clears cache safe memory,
- * 3. Initializes 'g_conn'.
- *
- * PARAMETERS: none
- *
- * RETURNS: OK or ERROR
- *
- ****************************************************************************/
-int atmMemInit()
-{
-  int i;
-  unsigned immr = CONFIG_SYS_IMMR;
-  int total_num_rbd = 0;
-  int total_num_tbd = 0;
-
-  memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
-
-  g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
-
-  for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
-    total_num_rbd += g_conn[i].num_rbd;
-    total_num_tbd += g_conn[i].num_tbd;
-  }
-
-  g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
-
-  g_atm.csram = &csram[0];
-  memset(&(g_atm.csram), 0x00, g_atm.csram_size);
-
-  g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4);
-  g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
-  g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
-
-  g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
-  g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
-  g_conn[0].ct_ptr = CT_PTR(immr);
-  g_conn[0].tcte_ptr = TCTE_PTR(immr);
-
-  return OK;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmIntInit
- *
- * DESCRIPTION:
- *
- * Initialization of the MPC860 ESAR Interrupt Queue.
- * This function
- * - clears all entries in the INT,
- * - sets the WRAP bit of the last INT entry,
- * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
- *   to the first INT entry.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARKS:
- *
- * - The INT resides in external cache safe memory.
- * - The base address of the INT is stored in g_atm.int_reload_ptr.
- * - The number of entries in the INT is given by NUM_INT_ENTRIES.
- * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
- *
- ****************************************************************************/
-void atmIntInit()
-{
-  int i;
-  for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
-  g_atm.int_reload_ptr[i] = INT_WRAP;
-  g_atm.int_serv_ptr = g_atm.int_reload_ptr;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmApcInit
- *
- * DESCRIPTION:
- *
- * This function initializes the following ATM Pace Controller related
- * data structures:
- *
- * - 1 MPHY Pointing Table (contains only one entry)
- * - 3 APC Parameter Tables (one PHY with 3 priorities)
- * - 3 APC Tables (one table for each priority)
- * - 1 Transmit Queue (one transmit queue per PHY)
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmApcInit()
-{
-  int i;
-  /* unsigned immr = CONFIG_SYS_IMMR; */
-  uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR);
-  struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR);
-  uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR);
-  uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR);
-  /***************************************************/
-  /* Initialize MPHY Pointing Table (only one entry) */
-  /***************************************************/
-  *mphypt_ptr = APCP_BASE;
-
-  /********************************************/
-  /* Initialize APC parameters for priority 1 */
-  /********************************************/
-  apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
-  apcp_ptr->apct_end1  =  APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
-  apcp_ptr->apct_ptr1  =  APCT_PRIO_1_BASE;
-  apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
-  apcp_ptr->etqbase    = TQ_BASE;
-  apcp_ptr->etqend     =  TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
-  apcp_ptr->etqaptr    = TQ_BASE;
-  apcp_ptr->etqtptr    = TQ_BASE;
-  apcp_ptr->apc_mi     = 8;
-  apcp_ptr->ncits      = 0x0100;   /* NCITS = 1 */
-  apcp_ptr->apcnt      = 0;
-  apcp_ptr->reserved1  = 0;
-  apcp_ptr->eapcst     = 0x2009;  /* LAST, ESAR, MPHY */
-  apcp_ptr->ptp_counter = 0;
-  apcp_ptr->ptp_txch   = 0;
-  apcp_ptr->reserved2  = 0;
-
-
-  /***************************************************/
-  /* Initialize APC Tables with empty slots (0xFFFF) */
-  /***************************************************/
-  for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
-
-  /************************/
-  /* Clear Transmit Queue */
-  /************************/
-  for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmAmtInit
- *
- * DESCRIPTION:
- *
- * This function clears the first entry in the Address Matching Table and
- * lets the first entry in the Address Pointing table point to the first
- * entry in the TCT table (i.e. the raw cell channel).
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARKS:
- *
- * The values for the AMBASE, AMEND and APBASE registers in SAR parameter
- * RAM are initialized by atmCpmInit().
- *
- ****************************************************************************/
-void atmAmtInit()
-{
-  unsigned immr = CONFIG_SYS_IMMR;
-
-  g_atm.am_top = AM_PTR(immr);
-  g_atm.ap_top = AP_PTR(immr);
-
-  *(g_atm.ap_top--) = CT_BASE;
-  *(g_atm.am_top--) = 0;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmCpmInit
- *
- * DESCRIPTION:
- *
- * This function initializes the Utopia Interface Parameter RAM Map
- * (SCC4, ATM Protocol) of the Communication Processor Modudule.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmCpmInit()
-{
-  unsigned immr = CONFIG_SYS_IMMR;
-
-  memset((char *)immr + 0x3F00, 0x00, 0xC0);
-
-  /*-----------------------------------------------------------------*/
-  /* RBDBASE - Receive buffer descriptors base address               */
-  /* The RBDs reside in cache safe external memory.                  */
-  /*-----------------------------------------------------------------*/
-  *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
-
-  /*-----------------------------------------------------------------*/
-  /* SRFCR - SAR receive function code                               */
-  /* 0-2 rsvd = 000                                                  */
-  /* 3-4 BO   = 11  Byte ordering (big endian).                      */
-  /* 5-7 FC   = 000 Value driven on the address type signals AT[1-3] */
-  /*                when the SDMA channel accesses memory.           */
-  /*-----------------------------------------------------------------*/
-  *SRFCR(immr) = 0x18;
-
-  /*-----------------------------------------------------------------*/
-  /* SRSTATE - SAR receive status                                    */
-  /* 0 EXT  = 0 Extended mode off.                                   */
-  /* 1 ACP  = 0 Valid only if EXT = 1.                               */
-  /* 2 EC   = 0 Standard 53-byte ATM cell.                           */
-  /* 3 SNC  = 0 In sync. Must be set to 0 during initialization.     */
-  /* 4 ESAR = 1 Enhanced SAR functionality enabled.                  */
-  /* 5 MCF  = 1 Management Cell Filter active.                       */
-  /* 6 SER  = 0 UTOPIA mode.                                         */
-  /* 7 MPY  = 1 Multiple PHY mode.                                   */
-  /*-----------------------------------------------------------------*/
-  *SRSTATE(immr) = 0x0D;
-
-  /*-----------------------------------------------------------------*/
-  /* MRBLR - Maximum receive buffer length register.                 */
-  /* Must be cleared for ATM operation (see also SMRBLR).            */
-  /*-----------------------------------------------------------------*/
-  *MRBLR(immr) = 0;
-
-  /*-----------------------------------------------------------------*/
-  /* RSTATE - SCC internal receive state parameters                  */
-  /* The first byte must be initialized with the value of SRFCR.     */
-  /*-----------------------------------------------------------------*/
-  *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
-
-  /*-----------------------------------------------------------------*/
-  /* STFCR - SAR transmit function code                              */
-  /* 0-2 rsvd = 000                                                  */
-  /* 3-4 BO   = 11  Byte ordering (big endian).                      */
-  /* 5-7 FC   = 000 Value driven on the address type signals AT[1-3] */
-  /*                when the SDMA channel accesses memory.           */
-  /*-----------------------------------------------------------------*/
-  *STFCR(immr) = 0x18;
-
-  /*-----------------------------------------------------------------*/
-  /* SRSTATE - SAR transmit status                                   */
-  /* 0 EXT  = 0 : Extended mode off                                  */
-  /* 1 rsvd = 0 :                                                    */
-  /* 2 EC   = 0 : Standard 53-byte ATM cell                          */
-  /* 3 rsvd = 0 :                                                    */
-  /* 4 ESAR = 1 : Enhanced SAR functionality enabled                 */
-  /* 5 rsvd = 0 :                                                    */
-  /* 6 SER  = 0 : UTOPIA mode                                        */
-  /* 7 MPY  = 1 : Multiple PHY mode                                  */
-  /*-----------------------------------------------------------------*/
-  *STSTATE(immr) = 0x09;
-
-  /*-----------------------------------------------------------------*/
-  /* TBDBASE - Transmit buffer descriptors base address              */
-  /* The TBDs reside in cache safe external memory.                  */
-  /*-----------------------------------------------------------------*/
-  *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
-
-  /*-----------------------------------------------------------------*/
-  /* TSTATE - SCC internal transmit state parameters                 */
-  /* The first byte must be initialized with the value of STFCR.     */
-  /*-----------------------------------------------------------------*/
-  *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
-
-  /*-----------------------------------------------------------------*/
-  /* CTBASE - Connection table base address                          */
-  /* Offset from the beginning of DPRAM (64-byte aligned).           */
-  /*-----------------------------------------------------------------*/
-  *CTBASE(immr) = CT_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* INTBASE - Interrupt queue base pointer.                         */
-  /* The interrupt queue resides in cache safe external memory.      */
-  /*-----------------------------------------------------------------*/
-  *INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
-
-  /*-----------------------------------------------------------------*/
-  /* INTPTR - Pointer into interrupt queue.                          */
-  /* Initialize to INTBASE.                                          */
-  /*-----------------------------------------------------------------*/
-  *INTPTR(immr) = *INTBASE(immr);
-
-  /*-----------------------------------------------------------------*/
-  /* C_MASK - Constant mask for CRC32                                */
-  /* Must be initialized to 0xDEBB20E3.                              */
-  /*-----------------------------------------------------------------*/
-  *C_MASK(immr) = 0xDEBB20E3;
-
-  /*-----------------------------------------------------------------*/
-  /* INT_ICNT - Interrupt threshold value                            */
-  /*-----------------------------------------------------------------*/
-  *INT_ICNT(immr) = 1;
-
-  /*-----------------------------------------------------------------*/
-  /* INT_CNT - Interrupt counter                                     */
-  /* Initalize to INT_ICNT. Decremented for each interrupt entry     */
-  /* reported in the interrupt queue. On zero an interrupt is        */
-  /* signaled to the host by setting the GINT bit in the event       */
-  /* register. The counter is reinitialized with INT_ICNT.           */
-  /*-----------------------------------------------------------------*/
-  *INT_CNT(immr) = *INT_ICNT(immr);
-
-  /*-----------------------------------------------------------------*/
-  /* SMRBLR - SAR maximum receive buffer length register.            */
-  /* Must be a multiple of 48 bytes. Common for all ATM connections. */
-  /*-----------------------------------------------------------------*/
-  *SMRBLR(immr) = SAR_RXB_SIZE;
-
-  /*-----------------------------------------------------------------*/
-  /* APCST - APC status register.                                    */
-  /* 0     rsvd 0                                                    */
-  /* 1-2   CSER 11  Initialize with the same value as NSER.          */
-  /* 3-4   NSER 11  Next serial or UTOPIA channel.                   */
-  /* 5-7   rsvd 000                                                  */
-  /* 8-10  rsvd 000                                                  */
-  /* 11    rsvd 0                                                    */
-  /* 12    ESAR 1   UTOPIA Level 2 MPHY enabled.                     */
-  /* 13    DIS  0   APC disable. Must be initiazed to 0.             */
-  /* 14    PL2  0   Not used.                                        */
-  /* 15    MPY  1   Multiple PHY mode on.                            */
-  /*-----------------------------------------------------------------*/
-  *APCST(immr) = 0x7809;
-
-  /*-----------------------------------------------------------------*/
-  /* APCPTR - Pointer to the APC parameter table                     */
-  /* In MPHY master mode this parameter points to the MPHY pointing  */
-  /* table. 2-byte aligned.                                          */
-  /*-----------------------------------------------------------------*/
-  *APCPTR(immr) = MPHYPT_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* HMASK - Header mask                                             */
-  /* Each incoming cell is masked with HMASK before being compared   */
-  /* to the entries in the address matching table.                   */
-  /*-----------------------------------------------------------------*/
-  *HMASK(immr) = AM_HMASK;
-
-  /*-----------------------------------------------------------------*/
-  /* AMBASE - Address matching table base address                    */
-  /*-----------------------------------------------------------------*/
-  *AMBASE(immr) = AM_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* AMEND - Address matching table end address                      */
-  /*-----------------------------------------------------------------*/
-  *AMEND(immr) = AM_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* APBASE - Address pointing table base address                    */
-  /*-----------------------------------------------------------------*/
-  *APBASE(immr) = AP_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* MPHYST - MPHY status register                                   */
-  /* 0-1   rsvd  00                                                  */
-  /* 2-6   NMPHY 00000 1 PHY                                         */
-  /* 7-9   rsvd  000                                                 */
-  /* 10-14 CMPHY 00000 Initialize with same value as NMPHY           */
-  /*-----------------------------------------------------------------*/
-  *MPHYST(immr) = 0x0000;
-
-  /*-----------------------------------------------------------------*/
-  /* TCTEBASE - Transmit connection table extension base address     */
-  /* Offset from the beginning of DPRAM (32-byte aligned).           */
-  /*-----------------------------------------------------------------*/
-  *TCTEBASE(immr) = TCTE_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* Clear not used registers.                                       */
-  /*-----------------------------------------------------------------*/
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmUtpInit
- *
- * DESCRIPTION:
- *
- * This function initializes the ATM interface for
- *
- * - UTOPIA mode
- * - muxed bus
- * - master operation
- * - multi PHY (because of a bug in the MPC860P rev. E.0)
- * - internal clock = SYSCLK / 2
- *
- * EXTERNAL EFFECTS:
- *
- * After calling this function, the MPC860ESAR UTOPIA bus is
- * active and uses the following ports/pins:
- *
- * Port    Pin  Signal   Description
- * ------  ---  -------  -------------------------------------------
- * PB[15]  R17  TxClav   Transmit cell available input/output signal
- * PC[15]  D16  RxClav   Receive cell available input/output signal
- * PD[15]  U17  UTPB[0]  UTOPIA bus bit 0 input/output signal
- * PD[14]  V19  UTPB[1]  UTOPIA bus bit 1 input/output signal
- * PD[13]  V18  UTPB[2]  UTOPIA bus bit 2 input/output signal
- * PD[12]  R16  UTPB[3]  UTOPIA bus bit 3 input/output signal
- * PD[11]  T16  RXENB    Receive enable input/output signal
- * PD[10]  W18  TXENB    Transmit enable input/output signal
- * PD[9]   V17  UTPCLK   UTOPIA clock input/output signal
- * PD[7]   T15  UTPB[4]  UTOPIA bus bit 4 input/output signal
- * PD[6]   V16  UTPB[5]  UTOPIA bus bit 5 input/output signal
- * PD[5]   U15  UTPB[6]  UTOPIA bus bit 6 input/output signal
- * PD[4]   U16  UTPB[7]  UTOPIA bus bit 7 input/output signal
- * PD[3]   W16  SOC      Start of cell input/output signal
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARK:
- *
- * The ATM parameters and data structures must be configured before
- * initializing the UTOPIA port. The UTOPIA port activates immediately
- * upon initialization, and if its associated data structures are not
- * initialized, the CPM will lock up.
- *
- ****************************************************************************/
-void atmUtpInit()
-{
-  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
-  volatile iop8xx_t      *iop    = &immap->im_ioport;
-  volatile car8xx_t	 *car    = &immap->im_clkrst;
-  volatile cpm8xx_t	 *cpm    = &immap->im_cpm;
-  int flag;
-
-  flag = disable_interrupts();
-
-  /*-----------------------------------------------------------------*/
-  /* SCCR - System Clock Control Register                            */
-  /*                                                                 */
-  /* The UTOPIA clock can be selected to be internal clock or        */
-  /* external clock (selected by the UTOPIA mode register).          */
-  /* In case of internal clock, the UTOPIA clock is derived from     */
-  /* the system frequency divided by two dividers.                   */
-  /* Bits 27-31 of the SCCR register are defined to control the      */
-  /* UTOPIA clock.                                                   */
-  /*                                                                 */
-  /* SCCR[27:29] DFUTP  Division factor. Divide the system clock     */
-  /*                    by 2^DFUTP.                                  */
-  /* SCCR[30:31] DFAUTP Additional division factor. Divide the       */
-  /*                    system clock by the following value:         */
-  /*                    00 = divide by 1                             */
-  /*                    00 = divide by 3                             */
-  /*                    10 = divide by 5                             */
-  /*                    11 = divide by 7                             */
-  /*                                                                 */
-  /* Note that the UTOPIA clock must be programmed as to operate     */
-  /* within the range SYSCLK/10 .. 50MHz.                            */
-  /*-----------------------------------------------------------------*/
-  car->car_sccr &= 0xFFFFFFE0;
-  car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
-
-  /*-----------------------------------------------------------------*/
-  /* RCCR - RISC Controller Configuration Register                   */
-  /*                                                                 */
-  /* RCCR[8]     DR1M IDMA Request 0 Mode                            */
-  /*                  0 = edge sensitive                             */
-  /*                  1 = level sensitive                            */
-  /* RCCR[9]     DR0M IDMA Request 0 Mode                            */
-  /*                  0 = edge sensitive                             */
-  /*                  1 = level sensitive                            */
-  /* RCCR[10:11] DRQP IDMA Request Priority                          */
-  /*                  00 = IDMA req. have more prio. than SCCs       */
-  /*                  01 = IDMA req. have less prio. then SCCs       */
-  /*                  10 = IDMA requests have the lowest prio.       */
-  /*                  11 = reserved                                  */
-  /*                                                                 */
-  /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
-  /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
-  /* higher priority.                                                */
-  /*-----------------------------------------------------------------*/
-  cpm->cp_rccr &= 0xFF0F;
-  cpm->cp_rccr |= 0x00D0;
-
-  /*-----------------------------------------------------------------*/
-  /* Port B - TxClav Signal                                          */
-  /*-----------------------------------------------------------------*/
-  cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
-  cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
-
-  /*-----------------------------------------------------------------*/
-  /* UTOPIA Mode Register                                            */
-  /*                                                                 */
-  /* - muxed bus (master operation only)                             */
-  /* - multi PHY (because of a bug in the MPC860P rev.E.0)           */
-  /* - internal clock                                                */
-  /* - no loopback                                                   */
-  /* - do no activate statistical counters                           */
-  /*-----------------------------------------------------------------*/
-  iop->utmode = 0x00000004; SYNC;
-
-  /*-----------------------------------------------------------------*/
-  /* Port D - UTOPIA Data and Control Signals                        */
-  /*                                                                 */
-  /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals       */
-  /* 11    RXENB     UTOPIA receive enable input/output signal       */
-  /* 10    TXENB     UTOPIA transmit enable input/output signal      */
-  /* 9     TUPCLK    UTOPIA clock input/output signal                */
-  /* 8     MII-MDC   Used by MII in simult. MII and UTOPIA operation */
-  /* 7-4   UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals       */
-  /* 3     SOC       UTOPIA Start of cell input/output signal        */
-  /* 2               Reserved                                        */
-  /* 1               Enable UTOPIA mode                              */
-  /* 0               Enable SAR                                      */
-  /*-----------------------------------------------------------------*/
-  iop->iop_pdpar |= 0xDF7F; SYNC;
-  iop->iop_pddir &= 0x2080; SYNC;
-
-  /*-----------------------------------------------------------------*/
-  /* Port C - RxClav Signal                                          */
-  /*-----------------------------------------------------------------*/
-  iop->iop_pcpar  |= 0x0001; /* PCPAR[15] = 1 */
-  iop->iop_pcdir  &= 0xFFFE; /* PCDIR[15] = 0 */
-  iop->iop_pcso   &= 0xFFFE; /* PCSO[15]  = 0 */
-
-  if (flag)
-    enable_interrupts();
-}
diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h
deleted file mode 100644
index cd5b45e..0000000
--- a/board/siemens/IAD210/atm.h
+++ /dev/null
@@ -1,287 +0,0 @@
-typedef unsigned char uint8;
-typedef unsigned short uint16;
-typedef unsigned int uint32;
-typedef volatile unsigned char vuint8;
-typedef volatile unsigned short vuint16;
-typedef volatile unsigned int vuint32;
-
-
-#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000
-
-#define ATM_DPRAM_BEGIN  (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000)
-#define NUM_CONNECTIONS  1
-#define SAR_RXB_SIZE     1584
-#define AM_HMASK         0x0FFFFFF0
-
-#define NUM_CT_ENTRIES           (NUM_CONNECTIONS)
-#define NUM_TCTE_ENTRIES         (NUM_CONNECTIONS)
-#define NUM_AM_ENTRIES           (NUM_CONNECTIONS+1)
-#define NUM_AP_ENTRIES           (NUM_CONNECTIONS+1)
-#define NUM_MPHYPT_ENTRIES       1
-#define NUM_APCP_ENTRIES         1
-#define NUM_APCT_PRIO_1_ENTRIES  146	/* Determines minimum rate */
-#define NUM_TQ_ENTRIES           12
-
-#define SIZE_OF_CT_ENTRY         64
-#define SIZE_OF_TCTE_ENTRY       32
-#define SIZE_OF_AM_ENTRY         4
-#define SIZE_OF_AP_ENTRY         2
-#define SIZE_OF_MPHYPT_ENTRY     2
-#define SIZE_OF_APCP_ENTRY       32
-#define SIZE_OF_APCT_ENTRY       2
-#define SIZE_OF_TQ_ENTRY         2
-
-#define CT_BASE           ((ATM_DPRAM_BEGIN + 63) & 0xFFC0)	/*64 */
-#define TCTE_BASE         (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY)	/*32 */
-#define APCP_BASE         (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY)	/*32 */
-#define AM_BEGIN          (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY)	/*4 */
-#define AM_BASE           (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
-#define AP_BEGIN          (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY)	/*2 */
-#define AP_BASE           (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
-#define MPHYPT_BASE       (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY)	/*2 */
-#define APCT_PRIO_1_BASE  (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY)	/*2 */
-#define TQ_BASE           (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY)	/*2 */
-#define ATM_DPRAM_SIZE    ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
-
-#define CT_PTR(base)      ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
-#define TCTE_PTR(base)    ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE))
-#define AM_PTR(base)      ((uint32 *)((char *)(base) + 0x2000 + AM_BASE))
-#define AP_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + AP_BASE))
-#define MPHYPT_PTR(base)  ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE))
-#define APCP_PTR(base)    ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE))
-#define APCT1_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE))
-#define APCT2_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE))
-#define APCT3_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE))
-#define TQ_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
-
-/* SAR registers */
-#define RBDBASE(base)	  ((vuint32 *)(base + 0x3F00))	/* Base address of RxBD-List */
-#define SRFCR(base)	  ((vuint8 *)(base + 0x3F04))	/* DMA Receive function code */
-#define SRSTATE(base)	  ((vuint8 *)(base + 0x3F05))	/* DMA Receive status */
-#define MRBLR(base)	  ((vuint16 *)(base + 0x3F06))	/* Init to 0 for ATM */
-#define RSTATE(base)	  ((vuint32 *)(base + 0x3F08))	/* Do not write to */
-#define R_CNT(base)	  ((vuint16 *)(base + 0x3F10))	/* Do not write to */
-#define STFCR(base)	  ((vuint8 *)(base + 0x3F12))	/* DMA Transmit function code */
-#define STSTATE(base)	  ((vuint8 *)(base + 0x3F13))	/* DMA Transmit status */
-#define TBDBASE(base)	  ((vuint32 *)(base + 0x3F14))	/* Base address of TxBD-List */
-#define TSTATE(base)	  ((vuint32 *)(base + 0x3F18))	/* Do not write to */
-#define COMM_CH(base)	  ((vuint16 *)(base + 0x3F1C))	/* Command channel */
-#define STCHNUM(base)	  ((vuint16 *)(base + 0x3F1E))	/* Do not write to */
-#define T_CNT(base)	  ((vuint16 *)(base + 0x3F20))	/* Do not write to */
-#define CTBASE(base)	  ((vuint16 *)(base + 0x3F22))	/* Base address of Connection-table */
-#define ECTBASE(base)	  ((vuint32 *)(base + 0x3F24))	/* Valid only for external Conn.-table */
-#define INTBASE(base)	  ((vuint32 *)(base + 0x3F28))	/* Base address of Interrupt-table */
-#define INTPTR(base)	  ((vuint32 *)(base + 0x3F2C))	/* Pointer to Interrupt-queue */
-#define C_MASK(base)	  ((vuint32 *)(base + 0x3F30))	/* CRC-mask */
-#define SRCHNUM(base)	  ((vuint16 *)(base + 0x3F34))	/* Do not write to */
-#define INT_CNT(base)	  ((vuint16 *)(base + 0x3F36))	/* Interrupt-Counter */
-#define INT_ICNT(base)	  ((vuint16 *)(base + 0x3F38))	/* Interrupt threshold */
-#define TSTA(base)	  ((vuint16 *)(base + 0x3F3A))	/* Time-stamp-address */
-#define OLDLEN(base)	  ((vuint16 *)(base + 0x3F3C))	/* Do not write to */
-#define SMRBLR(base)	  ((vuint16 *)(base + 0x3F3E))	/* SAR max RXBuffer length */
-#define EHEAD(base)	  ((vuint32 *)(base + 0x3F40))	/* Valid for serial mode */
-#define EPAYLOAD(base)	  ((vuint32 *)(base + 0x3F44))	/* Valid for serial mode */
-#define TQBASE(base)	  ((vuint16 *)(base + 0x3F48))	/* Base address of Tx queue */
-#define TQEND(base)	  ((vuint16 *)(base + 0x3F4A))	/* End address of Tx queue */
-#define TQAPTR(base)	  ((vuint16 *)(base + 0x3F4C))	/* TQ APC pointer */
-#define TQTPTR(base)	  ((vuint16 *)(base + 0x3F4E))	/* TQ Tx pointer */
-#define APCST(base)	  ((vuint16 *)(base + 0x3F50))	/* APC status */
-#define APCPTR(base)	  ((vuint16 *)(base + 0x3F52))	/* APC parameter pointer */
-#define HMASK(base)	  ((vuint32 *)(base + 0x3F54))	/* Header mask */
-#define AMBASE(base)	  ((vuint16 *)(base + 0x3F58))	/* Address match table base */
-#define AMEND(base)	  ((vuint16 *)(base + 0x3F5A))	/* Address match table end */
-#define APBASE(base)	  ((vuint16 *)(base + 0x3F5C))	/* Address match parameter */
-#define FLBASE(base)	  ((vuint32 *)(base + 0x3F54))	/* First-level table base */
-#define SLBASE(base)	  ((vuint32 *)(base + 0x3F58))	/* Second-level table base */
-#define FLMASK(base)	  ((vuint16 *)(base + 0x3F5C))	/* First-level mask */
-#define ECSIZE(base)	  ((vuint16 *)(base + 0x3F5E))	/* Valid for extended mode */
-#define APCT_REAL(base)	  ((vuint32 *)(base + 0x3F60))	/* APC 32 bit counter */
-#define R_PTR(base)	  ((vuint32 *)(base + 0x3F64))	/* Do not write to */
-#define RTEMP(base)	  ((vuint32 *)(base + 0x3F68))	/* Do not write to */
-#define T_PTR(base)	  ((vuint32 *)(base + 0x3F6C))	/* Do not write to */
-#define TTEMP(base)	  ((vuint32 *)(base + 0x3F70))	/* Do not write to */
-
-/* ESAR registers */
-#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80))	/* Perf.Mon.Timestamp */
-#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84))	/* Perf.Mon.Template */
-#define PMPTR(base)       ((vuint16 *)(base + 0x3F88))	/* Perf.Mon.Table */
-#define PMCHANNEL(base)	  ((vuint16 *)(base + 0x3F8A))	/* Perf.Mon.Channel */
-#define MPHYST(base)	  ((vuint16 *)(base + 0x3F90))	/* Multi-PHY Status */
-#define TCTEBASE(base)	  ((vuint16 *)(base + 0x3F92))	/* Internal TCT Extension Base */
-#define ETCTEBASE(base)	  ((vuint32 *)(base + 0x3F94))	/* External TCT Extension Base */
-#define COMM_CH2(base)	  ((vuint32 *)(base + 0x3F98))	/* 2nd command channel word */
-#define STATBASE(base)	  ((vuint16 *)(base + 0x3F9C))	/* Statistics table pointer */
-
-/* UTOPIA Mode Register */
-#define UTMODE(base)      (CAST(vuint32 *)(base + 0x0978))
-
-/* SAR commands */
-#define TRANSMIT_CHANNEL_ACTIVATE_CMD   0x0FC1
-#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1
-#define STOP_TRANSMIT_CMD               0x2FC1
-#define RESTART_TRANSMIT_CMD            0x3FC1
-#define STOP_RECEIVE_CMD                0x4FC1
-#define RESTART_RECEIVE_CMD             0x5FC1
-#define APC_BYPASS_CMD                  0x6FC1
-#define MEM_WRITE_CMD                   0x7FC1
-#define CPCR_FLG                        0x0001
-
-/* INT flags */
-#define INT_VALID	0x80000000
-#define INT_WRAP	0x40000000
-#define INT_APCO	0x00800000
-#define INT_TQF		0x00200000
-#define INT_RXF		0x00080000
-#define INT_BSY		0x00040000
-#define INT_TXB		0x00020000
-#define INT_RXB		0x00010000
-
-#define NUM_INT_ENTRIES   80
-#define SIZE_OF_INT_ENTRY 4
-
-struct apc_params_t {
-	vuint16 apct_base1;	/* APC Table - First Priority Base pointer */
-	vuint16 apct_end1;	/* First APC Table - Length */
-	vuint16 apct_ptr1;	/* First APC Table Pointer */
-	vuint16 apct_sptr1;	/* APC Table First Priority Service pointer */
-	vuint16 etqbase;	/* Enhanced Transmit Queue Base pointer */
-	vuint16 etqend;		/* Enhanced Transmit Queue End pointer */
-	vuint16 etqaptr;	/* Enhanced Transmit Queue APC pointer */
-	vuint16 etqtptr;	/* Enhanced Transmit Queue Transmitter pointer */
-	vuint16 apc_mi;		/* APC - Max Iteration */
-	vuint16 ncits;		/* Number of Cells In TimeSlot  */
-	vuint16 apcnt;		/* APC - N Timer */
-	vuint16 reserved1;	/* reserved */
-	vuint16 eapcst;		/* APC status */
-	vuint16 ptp_counter;	/* PTP queue length */
-	vuint16 ptp_txch;	/* PTP channel */
-	vuint16 reserved2;	/* reserved */
-};
-
-struct ct_entry_t {
-	/* RCT */
-	unsigned fhnt:1;
-	unsigned pm_rct:1;
-	unsigned reserved0:6;
-	unsigned hec:1;
-	unsigned clp:1;
-	unsigned cng_ncrc:1;
-	unsigned inf_rct:1;
-	unsigned cngi_ptp:1;
-	unsigned cdis_rct:1;
-	unsigned aal_rct:2;
-	uint16 rbalen;
-	uint32 rcrc;
-	uint32 rb_ptr;
-	uint16 rtmlen;
-	uint16 rbd_ptr;
-	uint16 rbase;
-	uint16 tstamp;
-	uint16 imask;
-	unsigned ft:2;
-	unsigned nim:1;
-	unsigned reserved1:2;
-	unsigned rpmt:6;
-	unsigned reserved2:5;
-	uint8 reserved3[8];
-	/* TCT */
-	unsigned reserved4:1;
-	unsigned pm_tct:1;
-	unsigned reserved5:6;
-	unsigned pc:1;
-	unsigned reserved6:2;
-	unsigned inf_tct:1;
-	unsigned cr10:1;
-	unsigned cdis_tct:1;
-	unsigned aal_tct:2;
-	uint16 tbalen;
-	uint32 tcrc;
-	uint32 tb_ptr;
-	uint16 ttmlen;
-	uint16 tbd_ptr;
-	uint16 tbase;
-	unsigned reserved7:5;
-	unsigned tpmt:6;
-	unsigned reserved8:3;
-	unsigned avcf:1;
-	unsigned act:1;
-	uint32 chead;
-	uint16 apcl;
-	uint16 apcpr;
-	unsigned out:1;
-	unsigned bnr:1;
-	unsigned tservice:2;
-	unsigned apcp:12;
-	uint16 apcpf;
-};
-
-struct tcte_entry_t {
-	unsigned res1:4;
-	unsigned scr:12;
-	uint16 scrf;
-	uint16 bt;
-	uint16 buptrh;
-	uint32 buptrl;
-	unsigned vbr2:1;
-	unsigned res2:15;
-	uint16 oobr;
-	uint16 res3[8];
-};
-
-#define SIZE_OF_RBD  12
-#define SIZE_OF_TBD  12
-
-struct atm_bd_t {
-	vuint16 flags;
-	vuint16 length;
-	unsigned char *buffer_ptr;
-	vuint16 cpcs_uu_cpi;
-	vuint16 reserved;
-};
-
-/* BD flags */
-#define EMPTY		0x8000
-#define READY		0x8000
-#define WRAP		0x2000
-#define INTERRUPT	0x1000
-#define LAST		0x0800
-#define FIRST		0x0400
-#define OAM             0x0400
-#define CONTINUOUS	0x0200
-#define HEC_ERROR	0x0080
-#define CELL_LOSS	0x0040
-#define CONGESTION	0x0020
-#define ABORT		0x0010
-#define LEN_ERROR	0x0002
-#define CRC_ERROR	0x0001
-
-struct atm_connection_t {
-	struct atm_bd_t *rbd_ptr;
-	int num_rbd;
-	struct atm_bd_t *tbd_ptr;
-	int num_tbd;
-	struct ct_entry_t *ct_ptr;
-	struct tcte_entry_t *tcte_ptr;
-	void *drv;
-	void (*notify) (void *drv, int event);
-};
-
-struct atm_driver_t {
-	int loaded;
-	int started;
-	char *csram;
-	int csram_size;
-	uint32 *am_top;
-	uint16 *ap_top;
-	uint32 *int_reload_ptr;
-	uint32 *int_serv_ptr;
-	struct atm_bd_t *rbd_base_ptr;
-	struct atm_bd_t *tbd_base_ptr;
-	unsigned linerate_in_bps;
-};
-
-extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
-extern struct atm_driver_t g_atm;
-
-extern int atmLoad (void);
-extern void atmUnload (void);
diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c
deleted file mode 100644
index c262e0f..0000000
--- a/board/siemens/IAD210/flash.c
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-  volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-  volatile memctl8xx_t *memctl = &immap->im_memctl;
-  unsigned long size;
-  int i;
-
-  /* Init: no FLASHes known */
-  for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-    flash_info[i].flash_id = FLASH_UNKNOWN;
-  }
-
-  /* Static FLASH Bank configuration here - FIXME XXX */
-
-  size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-  if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-    printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size, size<<20);
-  }
-
-
-  /* Remap FLASH according to real size */
-  memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-  memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-  /* Re-do sizing to get full correct info */
-  size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-  flash_info[0].size = size;
-
-  return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-  int i;
-
-  /* set up sector start address table */
-  if (info->flash_id & FLASH_BTYPE) {
-    /* set sector offsets for bottom boot block type	*/
-    info->start[0] = base + 0x00000000;
-    info->start[1] = base + 0x00008000;
-    info->start[2] = base + 0x0000C000;
-    info->start[3] = base + 0x00010000;
-    for (i = 4; i < info->sector_count; i++) {
-      info->start[i] = base + (i * 0x00020000) - 0x00060000;
-    }
-  } else {
-    /* set sector offsets for top boot block type		*/
-    i = info->sector_count - 1;
-    info->start[i--] = base + info->size - 0x00008000;
-    info->start[i--] = base + info->size - 0x0000C000;
-    info->start[i--] = base + info->size - 0x00010000;
-    for (; i >= 0; i--) {
-      info->start[i] = base + i * 0x00020000;
-    }
-  }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-  int i;
-
-  if (info->flash_id == FLASH_UNKNOWN) {
-    printf ("missing or unknown FLASH type\n");
-    return;
-  }
-
-  switch (info->flash_id & FLASH_VENDMASK) {
-  case FLASH_MAN_AMD:	printf ("AMD ");		break;
-  case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-  default:		printf ("Unknown Vendor ");	break;
-  }
-
-  switch (info->flash_id & FLASH_TYPEMASK) {
-  case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-    break;
-  case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-    break;
-  case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-    break;
-  case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-    break;
-  case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-    break;
-  case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-    break;
-  case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-    break;
-  case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-    break;
-  default:		printf ("Unknown Chip Type\n");
-    break;
-  }
-
-  printf ("  Size: %ld MB in %d Sectors\n",
-	  info->size >> 20, info->sector_count);
-
-  printf ("  Sector Start Addresses:");
-  for (i=0; i<info->sector_count; ++i) {
-    if ((i % 5) == 0)
-      printf ("\n   ");
-    printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-	    );
-  }
-  printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-  short i;
-  ulong value;
-  ulong base = (ulong)addr;
-
-
-  /* Write auto select command: read Manufacturer ID */
-  addr[0x0555] = 0x00AA00AA;
-  addr[0x02AA] = 0x00550055;
-  addr[0x0555] = 0x00900090;
-
-  value = addr[0];
-
-  switch (value) {
-  case AMD_MANUFACT:
-    info->flash_id = FLASH_MAN_AMD;
-    break;
-  case FUJ_MANUFACT:
-    info->flash_id = FLASH_MAN_FUJ;
-    break;
-  default:
-    info->flash_id = FLASH_UNKNOWN;
-    info->sector_count = 0;
-    info->size = 0;
-    return (0);			/* no or unknown flash	*/
-  }
-
-  value = addr[1];			/* device ID		*/
-
-  switch (value) {
-  case AMD_ID_LV400T:
-    info->flash_id += FLASH_AM400T;
-    info->sector_count = 11;
-    info->size = 0x00100000;
-    break;				/* => 1 MB		*/
-
-  case AMD_ID_LV400B:
-    info->flash_id += FLASH_AM400B;
-    info->sector_count = 11;
-    info->size = 0x00100000;
-    break;				/* => 1 MB		*/
-
-  case AMD_ID_LV800T:
-    info->flash_id += FLASH_AM800T;
-    info->sector_count = 19;
-    info->size = 0x00200000;
-    break;				/* => 2 MB		*/
-
-  case AMD_ID_LV800B:
-    info->flash_id += FLASH_AM800B;
-    info->sector_count = 19;
-    info->size = 0x00200000;
-    break;				/* => 2 MB		*/
-
-  case AMD_ID_LV160T:
-    info->flash_id += FLASH_AM160T;
-    info->sector_count = 35;
-    info->size = 0x00400000;
-    break;				/* => 4 MB		*/
-
-  case AMD_ID_LV160B:
-    info->flash_id += FLASH_AM160B;
-    info->sector_count = 35;
-    info->size = 0x00400000;
-    break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-  case AMD_ID_LV320T:
-    info->flash_id += FLASH_AM320T;
-    info->sector_count = 67;
-    info->size = 0x00800000;
-    break;				/* => 8 MB		*/
-
-  case AMD_ID_LV320B:
-    info->flash_id += FLASH_AM320B;
-    info->sector_count = 67;
-    info->size = 0x00800000;
-    break;				/* => 8 MB		*/
-#endif
-  default:
-    info->flash_id = FLASH_UNKNOWN;
-    return (0);			/* => no or unknown flash */
-
-  }
-
-  /* set up sector start address table */
-  if (info->flash_id & FLASH_BTYPE) {
-    /* set sector offsets for bottom boot block type	*/
-    info->start[0] = base + 0x00000000;
-    info->start[1] = base + 0x00008000;
-    info->start[2] = base + 0x0000C000;
-    info->start[3] = base + 0x00010000;
-    for (i = 4; i < info->sector_count; i++) {
-      info->start[i] = base + (i * 0x00020000) - 0x00060000;
-    }
-  } else {
-    /* set sector offsets for top boot block type		*/
-    i = info->sector_count - 1;
-    info->start[i--] = base + info->size - 0x00008000;
-    info->start[i--] = base + info->size - 0x0000C000;
-    info->start[i--] = base + info->size - 0x00010000;
-    for (; i >= 0; i--) {
-      info->start[i] = base + i * 0x00020000;
-    }
-  }
-
-  /* check for protected sectors */
-  for (i = 0; i < info->sector_count; i++) {
-    /* read sector protection at sector address, (A7 .. A0) = 0x02 */
-    /* D0 = 1 if protected */
-    addr = (volatile unsigned long *)(info->start[i]);
-    info->protect[i] = addr[2] & 1;
-  }
-
-  /*
-   * Prevent writes to uninitialized FLASH.
-   */
-  if (info->flash_id != FLASH_UNKNOWN) {
-    addr = (volatile unsigned long *)info->start[0];
-
-    *addr = 0x00F000F0;	/* reset bank */
-  }
-
-  return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-  vu_long *addr = (vu_long*)(info->start[0]);
-  int flag, prot, sect, l_sect;
-  ulong start, now, last;
-
-  if ((s_first < 0) || (s_first > s_last)) {
-    if (info->flash_id == FLASH_UNKNOWN) {
-      printf ("- missing\n");
-    } else {
-      printf ("- no sectors to erase\n");
-    }
-    return 1;
-  }
-
-  if ((info->flash_id == FLASH_UNKNOWN) ||
-      (info->flash_id > FLASH_AMD_COMP)) {
-    printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-    return 1;
-  }
-
-  prot = 0;
-  for (sect=s_first; sect<=s_last; ++sect) {
-    if (info->protect[sect]) {
-      prot++;
-    }
-  }
-
-  if (prot) {
-    printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-  } else {
-    printf ("\n");
-  }
-
-  l_sect = -1;
-
-  /* Disable interrupts which might cause a timeout here */
-  flag = disable_interrupts();
-
-  addr[0x0555] = 0x00AA00AA;
-  addr[0x02AA] = 0x00550055;
-  addr[0x0555] = 0x00800080;
-  addr[0x0555] = 0x00AA00AA;
-  addr[0x02AA] = 0x00550055;
-
-  /* Start erase on unprotected sectors */
-  for (sect = s_first; sect<=s_last; sect++) {
-    if (info->protect[sect] == 0) {	/* not protected */
-      addr = (vu_long*)(info->start[sect]);
-      addr[0] = 0x00300030;
-      l_sect = sect;
-    }
-  }
-
-  /* re-enable interrupts if necessary */
-  if (flag)
-    enable_interrupts();
-
-  /* wait at least 80us - let's wait 1 ms */
-  udelay (1000);
-
-  /*
-   * We wait for the last triggered sector
-   */
-  if (l_sect < 0)
-    goto DONE;
-
-  start = get_timer (0);
-  last  = start;
-  addr = (vu_long*)(info->start[l_sect]);
-  while ((addr[0] & 0x00800080) != 0x00800080) {
-    if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-      printf ("Timeout\n");
-      return 1;
-    }
-    /* show that we're waiting */
-    if ((now - last) > 1000) {	/* every second */
-      putc ('.');
-      last = now;
-    }
-  }
-
- DONE:
-  /* reset to read mode */
-  addr = (volatile unsigned long *)info->start[0];
-  addr[0] = 0x00F000F0;	/* reset bank */
-
-  printf (" done\n");
-  return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-  ulong cp, wp, data;
-  int i, l, rc;
-
-  wp = (addr & ~3);	/* get lower word aligned address */
-
-  /*
-   * handle unaligned start bytes
-   */
-  if ((l = addr - wp) != 0) {
-    data = 0;
-    for (i=0, cp=wp; i<l; ++i, ++cp) {
-      data = (data << 8) | (*(uchar *)cp);
-    }
-    for (; i<4 && cnt>0; ++i) {
-      data = (data << 8) | *src++;
-      --cnt;
-      ++cp;
-    }
-    for (; cnt==0 && i<4; ++i, ++cp) {
-      data = (data << 8) | (*(uchar *)cp);
-    }
-
-    if ((rc = write_word(info, wp, data)) != 0) {
-      return (rc);
-    }
-    wp += 4;
-  }
-
-  /*
-   * handle word aligned part
-   */
-  while (cnt >= 4) {
-    data = 0;
-    for (i=0; i<4; ++i) {
-      data = (data << 8) | *src++;
-    }
-    if ((rc = write_word(info, wp, data)) != 0) {
-      return (rc);
-    }
-    wp  += 4;
-    cnt -= 4;
-  }
-
-  if (cnt == 0) {
-    return (0);
-  }
-
-  /*
-   * handle unaligned tail bytes
-   */
-  data = 0;
-  for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-    data = (data << 8) | *src++;
-    --cnt;
-  }
-  for (; i<4; ++i, ++cp) {
-    data = (data << 8) | (*(uchar *)cp);
-  }
-
-  return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-  vu_long *addr = (vu_long*)(info->start[0]);
-  ulong start;
-  int flag;
-
-  /* Check if Flash is (sufficiently) erased */
-  if ((*((vu_long *)dest) & data) != data) {
-    return (2);
-  }
-  /* Disable interrupts which might cause a timeout here */
-  flag = disable_interrupts();
-
-  addr[0x0555] = 0x00AA00AA;
-  addr[0x02AA] = 0x00550055;
-  addr[0x0555] = 0x00A000A0;
-
-  *((vu_long *)dest) = data;
-
-  /* re-enable interrupts if necessary */
-  if (flag)
-    enable_interrupts();
-
-  /* data polling for D7 */
-  start = get_timer (0);
-  while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-    if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-      return (1);
-    }
-  }
-  return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds
deleted file mode 100644
index 0e78e4f..0000000
--- a/board/siemens/IAD210/u-boot.lds
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    net/libnet.o			(.text*)
-    drivers/rtc/librtc.o		(.text*)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile
deleted file mode 100644
index 07db9d4..0000000
--- a/board/siemens/SCM/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common $(obj)../../tqc/tqm8xx)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= scm.o flash.o fpga_scm.o ../common/fpga.o \
-	  ../../tqc/tqm8xx/load_sernum_ethaddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c
deleted file mode 100644
index 4a6d538..0000000
--- a/board/siemens/SCM/flash.c
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Flash Routines for AMD devices on the TQM8260 board
- *
- *--------------------------------------------------------------------
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
-#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-/*-----------------------------------------------------------------------
- */
-void flash_reset (void)
-{
-	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
-		V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
-		V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_get_size (ulong baseaddr, flash_info_t * info)
-{
-	short i;
-	unsigned long flashtest_h, flashtest_l;
-
-	/* Write auto select command sequence and test FLASH answer */
-	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
-	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
-	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
-	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
-
-	flashtest_h = V_ULONG (baseaddr);	/* manufacturer ID     */
-	flashtest_l = V_ULONG (baseaddr + 4);
-
-	switch ((int) flashtest_h) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash     */
-	}
-
-	flashtest_h = V_ULONG (baseaddr + 8);	/* device ID           */
-	flashtest_l = V_ULONG (baseaddr + 12);
-	if (flashtest_h != flashtest_l) {
-		info->flash_id = FLASH_UNKNOWN;
-	} else {
-		switch (flashtest_h) {
-		case AMD_ID_LV800T:
-			info->flash_id += FLASH_AM800T;
-			info->sector_count = 19;
-			info->size = 0x00400000;
-			break;			/* 4 * 1 MB = 4 MB  */
-		case AMD_ID_LV800B:
-			info->flash_id += FLASH_AM800B;
-			info->sector_count = 19;
-			info->size = 0x00400000;
-			break;			/* 4 * 1 MB = 4 MB  */
-		case AMD_ID_LV160T:
-			info->flash_id += FLASH_AM160T;
-			info->sector_count = 35;
-			info->size = 0x00800000;
-			break;			/* 4 * 2 MB = 8 MB  */
-		case AMD_ID_LV160B:
-			info->flash_id += FLASH_AM160B;
-			info->sector_count = 35;
-			info->size = 0x00800000;
-			break;			/* 4 * 2 MB = 8 MB  */
-		case AMD_ID_DL322T:
-			info->flash_id += FLASH_AMDL322T;
-			info->sector_count = 71;
-			info->size = 0x01000000;
-			break;			/* 4 * 4 MB = 16 MB */
-		case AMD_ID_DL322B:
-			info->flash_id += FLASH_AMDL322B;
-			info->sector_count = 71;
-			info->size = 0x01000000;
-			break;			/* 4 * 4 MB = 16 MB */
-		case AMD_ID_DL323T:
-			info->flash_id += FLASH_AMDL323T;
-			info->sector_count = 71;
-			info->size = 0x01000000;
-			break;			/* 4 * 4 MB = 16 MB */
-		case AMD_ID_DL323B:
-			info->flash_id += FLASH_AMDL323B;
-			info->sector_count = 71;
-			info->size = 0x01000000;
-			break;			/* 4 * 4 MB = 16 MB */
-		case AMD_ID_LV640U:
-			info->flash_id += FLASH_AM640U;
-			info->sector_count = 128;
-			info->size = 0x02000000;
-			break;			/* 4 * 8 MB = 32 MB */
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);		/* no or unknown flash     */
-		}
-	}
-
-	if (flashtest_h == AMD_ID_LV640U) {
-
-		/* set up sector start adress table (uniform sector type) */
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = baseaddr + (i * 0x00040000);
-
-	} else if (info->flash_id & FLASH_BTYPE) {
-
-		/* set up sector start adress table (bottom sector type) */
-		info->start[0] = baseaddr + 0x00000000;
-		info->start[1] = baseaddr + 0x00010000;
-		info->start[2] = baseaddr + 0x00018000;
-		info->start[3] = baseaddr + 0x00020000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
-		}
-
-	} else {
-
-		/* set up sector start adress table (top sector type) */
-		i = info->sector_count - 1;
-		info->start[i--] = baseaddr + info->size - 0x00010000;
-		info->start[i--] = baseaddr + info->size - 0x00018000;
-		info->start[i--] = baseaddr + info->size - 0x00020000;
-		for (; i >= 0; i--) {
-			info->start[i] = baseaddr + i * 0x00040000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
-			(V_ULONG (info->start[i] + 20) & 0x00010001)) {
-			info->protect[i] = 1;	/* D0 = 1 if protected */
-		} else {
-			info->protect[i] = 0;
-		}
-	}
-
-	flash_reset ();
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-	unsigned long size_b0 = 0;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here (only one bank) */
-
-	size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
-	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-				size_b0, size_b0 >> 20);
-	}
-
-	/*
-	 * protect monitor and environment sectors
-	 */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
-	return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf ("AMD ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf ("FUJITSU ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM800T:
-		printf ("29LV800T (8 M, top sector)\n");
-		break;
-	case FLASH_AM800B:
-		printf ("29LV800T (8 M, bottom sector)\n");
-		break;
-	case FLASH_AM160T:
-		printf ("29LV160T (16 M, top sector)\n");
-		break;
-	case FLASH_AM160B:
-		printf ("29LV160B (16 M, bottom sector)\n");
-		break;
-	case FLASH_AMDL322T:
-		printf ("29DL322T (32 M, top sector)\n");
-		break;
-	case FLASH_AMDL322B:
-		printf ("29DL322B (32 M, bottom sector)\n");
-		break;
-	case FLASH_AMDL323T:
-		printf ("29DL323T (32 M, top sector)\n");
-		break;
-	case FLASH_AMDL323B:
-		printf ("29DL323B (32 M, bottom sector)\n");
-		break;
-	case FLASH_AM640U:
-		printf ("29LV640D (64 M, uniform sector)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
-	udelay (1000);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			V_ULONG (info->start[sect]) = 0x00300030;
-			V_ULONG (info->start[sect] + 4) = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last = start;
-	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
-	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
-	{
-		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			serial_putc ('.');
-			last = now;
-		}
-	}
-
-  DONE:
-	/* reset to read mode */
-	flash_reset ();
-
-	printf (" done\n");
-	return 0;
-}
-
-static int write_dword (flash_info_t *, ulong, unsigned char *);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong dp;
-	static unsigned char bb[8];
-	int i, l, rc, cc = cnt;
-
-	dp = (addr & ~7);		/* get lower dword aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - dp) != 0) {
-		for (i = 0; i < 8; i++)
-			bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
-		if ((rc = write_dword (info, dp, bb)) != 0) {
-			return (rc);
-		}
-		dp += 8;
-		cc -= 8 - l;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cc >= 8) {
-		if ((rc = write_dword (info, dp, src)) != 0) {
-			return (rc);
-		}
-		dp += 8;
-		src += 8;
-		cc -= 8;
-	}
-
-	if (cc <= 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	for (i = 0; i < 8; i++) {
-		bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
-	}
-	return (write_dword (info, dp, bb));
-}
-
-/*-----------------------------------------------------------------------
- * Write a dword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
-{
-	ulong start, cl, ch;
-	int flag, i;
-
-	for (ch = 0, i = 0; i < 4; i++)
-		ch = (ch << 8) + *pdata++;	/* high word    */
-	for (cl = 0, i = 0; i < 4; i++)
-		cl = (cl << 8) + *pdata++;	/* low word */
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *) dest) & ch) != ch
-		|| (*((vu_long *) (dest + 4)) & cl) != cl) {
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
-	V_ULONG (dest) = ch;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
-	V_ULONG (dest + 4) = cl;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
-		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c
deleted file mode 100644
index acd9c15..0000000
--- a/board/siemens/SCM/fpga_scm.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <mpc8260.h>
-#include <common.h>
-#include "../common/fpga.h"
-
-fpga_t fpga_list[] = {
-	{"FIOX", CONFIG_SYS_FIOX_BASE,
-	 CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE}
-	,
-	{"FDOHM", CONFIG_SYS_FDOHM_BASE,
-	 CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE}
-};
-int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
-
-
-ulong fpga_control (fpga_t * fpga, int cmd)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
-	switch (cmd) {
-	case FPGA_INIT_IS_HIGH:
-		immr->im_ioport.iop_pdird &= ~fpga->init_mask;	/* input */
-		return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
-
-	case FPGA_INIT_SET_LOW:
-		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
-		immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
-		break;
-
-	case FPGA_INIT_SET_HIGH:
-		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
-		immr->im_ioport.iop_pdatd |= fpga->init_mask;
-		break;
-
-	case FPGA_PROG_SET_LOW:
-		immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
-		break;
-
-	case FPGA_PROG_SET_HIGH:
-		immr->im_ioport.iop_pdatd |= fpga->prog_mask;
-		break;
-
-	case FPGA_DONE_IS_HIGH:
-		return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
-
-	case FPGA_READ_MODE:
-		break;
-
-	case FPGA_LOAD_MODE:
-		break;
-
-	case FPGA_GET_ID:
-		if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) {
-			ulong ver =
-				*(volatile ulong *) (fpga->conf_base + 0x10);
-			return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
-		} else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) {
-			return (*(volatile ushort *) fpga->conf_base) & 0xff;
-		} else {
-			return *(volatile ulong *) fpga->conf_base;
-		}
-
-	case FPGA_INIT_PORTS:
-		immr->im_ioport.iop_ppard &= ~fpga->init_mask;	/* INIT I/O */
-		immr->im_ioport.iop_psord &= ~fpga->init_mask;
-		immr->im_ioport.iop_pdird &= ~fpga->init_mask;
-
-		immr->im_ioport.iop_ppard &= ~fpga->prog_mask;	/* PROG Output */
-		immr->im_ioport.iop_psord &= ~fpga->prog_mask;
-		immr->im_ioport.iop_pdird |= fpga->prog_mask;
-
-		immr->im_ioport.iop_ppard &= ~fpga->done_mask;	/* DONE Input */
-		immr->im_ioport.iop_psord &= ~fpga->done_mask;
-		immr->im_ioport.iop_pdird &= ~fpga->done_mask;
-
-		break;
-
-	}
-	return 0;
-}
diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c
deleted file mode 100644
index 461b56e..0000000
--- a/board/siemens/SCM/scm.c
+++ /dev/null
@@ -1,541 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <linux/compiler.h>
-
-#include "scm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void config_scoh_cs(void);
-extern int  fpga_init(void);
-
-#if 0
-#define DEBUGF(fmt,args...)   printf (fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
-	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
-	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
-	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
-	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
-	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
-	/* PA25 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA24 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA23 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA22 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
-	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
-	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
-	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
-	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
-	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1]*/
-	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
-	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
-	/* PA13 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA12 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA11 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA10 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA9  */ {   1,   1,   1,   1,   0,   0   }, /* TDM_A1 L1TXD0 */
-	/* PA8  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RXD0 */
-	/* PA7  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1TSYNC */
-	/* PA6  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RSYNC */
-	/* PA5  */ {   1,   0,   0,   0,   0,   0   }, /* FIOX_FPGA_PR */
-	/* PA4  */ {   1,   0,   0,   0,   0,   0   }, /* DOHM_FPGA_PR */
-	/* PA3  */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK4 */
-	/* PA2  */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK4 */
-	/* PA1  */ {   0,   0,   0,   1,   0,   0   },
-	/* PA0  */ {   1,   0,   0,   0,   0,   0   }  /* BUSY */
-    },
-
-    /* Port B configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MIN */
-	/* PB30 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MAJ */
-	/* PB29 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MIN */
-	/* PB28 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MAJ */
-	/* PB27 */ {   0,   1,   0,   0,   0,   0   },
-	/* PB26 */ {   0,   1,   0,   0,   0,   0   },
-	/* PB25 */ {   1,   0,   0,   1,   0,   0   }, /* LED_GREEN_L */
-	/* PB24 */ {   1,   0,   0,   1,   0,   0   }, /* LED_RED_L */
-	/* PB23 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TXD */
-	/* PB22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RXD */
-	/* PB21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TSYNC */
-	/* PB20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RSYNC */
-	/* PB19 */ {   1,   0,   0,   0,   0,   0   }, /* UID */
-	/* PB18 */ {   0,   1,   0,   0,   0,   0   },
-	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
-	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
-	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
-	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
-	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
-	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
-	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
-	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
-	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
-	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
-	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
-	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
-	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
-	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK1 */
-	/* PC30 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK1 */
-	/* PC29 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK3 */
-	/* PC28 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK3 */
-	/* PC27 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK2 */
-	/* PC26 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK2 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   },
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   },
-	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
-	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
-	/* PC19 */ {   0,   1,   0,   0,   0,   0   },
-	/* PC18 */ {   0,   1,   0,   0,   0,   0   },
-	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
-	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
-	/* PC15 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   },
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* RES_PHY_L */
-	/* PC12 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC10 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC9  */ {   0,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TSYNC */
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* FEP_RDY */
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* UC4_ALARM_L */
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* UC3_ALARM_L */
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* UC2_ALARM_L */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* RES_MISC_L */
-	/* PC2  */ {   0,   0,   0,   1,   0,   0   }, /* RES_OH_L */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* RES_DOHM_L */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* RES_FIOX_L */
-    },
-
-    /* Port D configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* INIT_F */
-	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_F */
-	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* INIT_D */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_D */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   },
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   },
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   },
-	/* PD22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TXD */
-	/* PD21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RXD */
-	/* PD20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RSYNC */
-	/* PD19 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPISEL */
-	/* PD18 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPICLK */
-	/* PD17 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSI */
-	/* PD16 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSO */
-#if defined(CONFIG_SOFT_I2C)
-	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
-	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#else /* normal I/O port pins */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#endif
-#endif
-	/* PD13 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TXD */
-	/* PD12 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RXD */
-	/* PD11 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TSYNC */
-	/* PD10 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RSYNC */
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   },
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   },
-	/* PD5  */ {   0,   0,   0,   1,   0,   0   }, /* PROG_F */
-	/* PD4  */ {   0,   0,   0,   1,   0,   0   }, /* PROG_D */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof (str));
-
-	puts ("Board: ");
-
-	if (!i || strncmp (str, "TQM8260", 7)) {
-		puts ("### No HW ID - assuming TQM8260\n");
-		return (0);
-	}
-
-	puts (str);
-	putc ('\n');
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
-						  ulong orx, volatile uchar * base)
-{
-	volatile uchar c = 0xff;
-	volatile uint *sdmr_ptr;
-	volatile uint *orx_ptr;
-	ulong maxsize, size;
-	int i;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (1 + (~orx | 0x7fff)) / 2;
-
-	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
-	 * we are configuring CS1 if base != 0
-	 */
-	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
-	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
-
-	*orx_ptr = orx;
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
-	*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*base = c;
-
-	size = get_ram_size((long *)base, maxsize);
-
-	*orx_ptr = orx | ~(size - 1);
-
-	return (size);
-}
-
-/*
- * Test Power-On-Reset.
- */
-int power_on_reset (void)
-{
-	/* Test Reset Status Register */
-	return gd->reset_status & RSR_CSRS ? 0 : 1;
-}
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	long size8, size9;
-#endif
-	long psize, lsize;
-
-	psize = 16 * 1024 * 1024;
-	lsize = 0;
-
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#if 0							/* Just for debugging */
-#define	prt_br_or(brX,orX) do {				\
-    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
-    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
-    printf ("\n"					\
-	    #brX " 0x%08x  " #orX " 0x%08x "		\
-	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
-	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
-	start, start+sizem, (sizem+1)>>20);		\
-    } while (0)
-	prt_br_or (br0, or0);
-	prt_br_or (br1, or1);
-	prt_br_or (br2, or2);
-	prt_br_or (br3, or3);
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-	/* 60x SDRAM setup:
-	 */
-	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
-					  (uchar *) CONFIG_SYS_SDRAM_BASE);
-	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
-					  (uchar *) CONFIG_SYS_SDRAM_BASE);
-
-	if (size8 < size9) {
-		psize = size9;
-		printf ("(60x:9COL - %ld MB, ", psize >> 20);
-	} else {
-		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
-						  (uchar *) CONFIG_SYS_SDRAM_BASE);
-		printf ("(60x:8COL - %ld MB, ", psize >> 20);
-	}
-
-	/* Local SDRAM setup:
-	 */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
-	memctl->memc_lsrt = CONFIG_SYS_LSRT;
-	size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
-					  (uchar *) SDRAM_BASE2_PRELIM);
-	size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
-					  (uchar *) SDRAM_BASE2_PRELIM);
-
-	if (size8 < size9) {
-		lsize = size9;
-		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
-	} else {
-		lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
-						  (uchar *) SDRAM_BASE2_PRELIM);
-		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
-	}
-
-#if 0
-	/* Set up BR2 so that the local SDRAM goes
-	 * right after the 60x SDRAM
-	 */
-	memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
-			(CONFIG_SYS_SDRAM_BASE + psize);
-#endif
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	icache_enable ();
-
-	config_scoh_cs ();
-
-	return (psize);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void config_scoh_cs (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immr->im_memctl;
-	volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE;
-	__maybe_unused volatile uint tmp, i;
-
-	/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
-	memctl->memc_or3 = CONFIG_SYS_CAN0_OR3;
-	memctl->memc_br3 = CONFIG_SYS_CAN0_BR3;
-	/* Initialize OR4 / BR4 for CAN Bus Controller 1 */
-	memctl->memc_or4 = CONFIG_SYS_CAN1_OR4;
-	memctl->memc_br4 = CONFIG_SYS_CAN1_BR4;
-
-	/* Initialize MAMR to write in the array at address 0x0 */
-	memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
-
-	/* Initialize UPMA for CAN: single read */
-	memctl->memc_mdr = 0xcffeec00;
-	udelay (1);					/* Necessary to have the data correct in the UPM array!!!! */
-	/* The read on the CAN controller write the data of mdr in UPMA array. */
-	/* The index to the array will be incremented automatically
-	   through this read */
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcfc00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcfc00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0xfffdec07;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-
-	/* Initialize MAMR to write in the array at address 0x18 */
-	memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
-
-	/* Initialize UPMA for CAN: single write */
-	memctl->memc_mdr = 0xfcffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00ffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00ffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00ffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00ffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00fffc00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00fffc00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x30ffec07;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	/* Initialize MAMR */
-	memctl->memc_mamr = MxMR_GPL_x4DIS;	/* GPL_B4 ouput line Disable */
-
-
-	/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
-	memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5;
-	memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5;
-	/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
-	memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6;
-	memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6;
-
-	/* Initialize OR7 / BR7 for the Glue Logic */
-	memctl->memc_or7 = CONFIG_SYS_FIOX_OR7;
-	memctl->memc_br7 = CONFIG_SYS_FIOX_BR7;
-
-	/* Initialize OR8 / BR8 for the DOH Logic */
-	memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8;
-	memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8;
-
-	DEBUGF ("OR0 %08x   BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
-	DEBUGF ("OR1 %08x   BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
-	DEBUGF ("OR2 %08x   BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
-	DEBUGF ("OR3 %08x   BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
-	DEBUGF ("OR4 %08x   BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
-	DEBUGF ("OR5 %08x   BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
-	DEBUGF ("OR6 %08x   BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
-	DEBUGF ("OR7 %08x   BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
-	DEBUGF ("OR8 %08x   BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
-
-	DEBUGF ("UPMA  addr 0x0\n");
-	memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
-	for (i = 0; i < 0x8; i++) {
-		tmp = can->cpu_interface;
-		udelay (1);
-		DEBUGF (" %08x ", memctl->memc_mdr);
-	}
-	DEBUGF ("\nUPMA  addr 0x18\n");
-	memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
-	for (i = 0; i < 0x8; i++) {
-		tmp = can->cpu_interface;
-		udelay (1);
-		DEBUGF (" %08x ", memctl->memc_mdr);
-	}
-	DEBUGF ("\n");
-	memctl->memc_mamr = MxMR_GPL_x4DIS;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r (void)
-{
-	fpga_init ();
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/SCM/scm.h b/board/siemens/SCM/scm.h
deleted file mode 100644
index cb5e03e..0000000
--- a/board/siemens/SCM/scm.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SCM_H
-#define __SCM_H
-
-/*----------------*/
-/* CAN Structures */
-/*----------------*/
-
-/* Message */
-struct can_msg {
-    uchar	ctrl_0;
-    uchar	ctrl_1;
-    uchar	arbit_0;
-    uchar	arbit_1;
-    uchar	arbit_2;
-    uchar	arbit_3;
-    uchar	config;
-    uchar	data[8];
-} __attribute__ ((packed));
-
-typedef struct can_msg can_msg_t;
-
-/* CAN Register */
-typedef struct can_reg {
-    uchar	ctrl;
-    uchar	status;
-    uchar	cpu_interface;
-    uchar	resv0;
-    ushort	high_speed_rd;
-    ushort	gbl_mask_std;
-    uint	gbl_mask_extd;
-    uint	msg15_mask;
-    can_msg_t	msg1;
-    uchar	clkout;
-    can_msg_t	msg2;
-    uchar	bus_config;
-    can_msg_t	msg3;
-    uchar	bit_timing_0;
-    can_msg_t	msg4;
-    uchar	bit_timing_1;
-    can_msg_t	msg5;
-    uchar	interrupt;
-    can_msg_t	msg6;
-    uchar	resv1;
-    can_msg_t	msg7;
-    uchar	resv2;
-    can_msg_t	msg8;
-    uchar	resv3;
-    can_msg_t	msg9;
-    uchar	p1conf;
-    can_msg_t	msg10;
-    uchar	p2conf;
-    can_msg_t	msg11;
-    uchar	p1in;
-    can_msg_t	msg12;
-    uchar	p2in;
-    can_msg_t	msg13;
-    uchar	p1out;
-    can_msg_t	msg14;
-    uchar	p2out;
-    can_msg_t	msg15;
-    uchar	ser_res_addr;
-    uchar	resv_cs[0x8000-0x100];	/* 0x8000 is the min size for CS */
-} can_reg_t;
-
-
-#endif /* __SCM_H */
diff --git a/board/siemens/common/README b/board/siemens/common/README
deleted file mode 100644
index 7f1c8cd..0000000
--- a/board/siemens/common/README
+++ /dev/null
@@ -1,27 +0,0 @@
-CCM/SCM-Ergaenzungen fuer U-Boot und Linux:
--------------------------------------------
-
-Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs:
-
-  => help fpga
-  fpga fpga status [name] - print FPGA status
-  fpga reset  [name] - reset FPGA
-  fpga load [name] addr - load FPGA configuration data
-
-Der Name kann beim CCM-Module auch weggelassen werden.
-Die Laengenangabe und damit "puma_len" ist nicht mehr
-noetig:
-
-  => fpga load puma 40600000
-  FPGA load PUMA: addr 40600000: (00000005)... done
-
-Die MTD-Partitionierung kann nun mittels "bootargs" ueber-
-geben werden:
-
-  => printenv addmtd
-  addmtd=setenv bootargs ${bootargs}
-    mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2)
-
-Die Portierung auf SMC ist natuerlich noch nicht getestet.
-
-Wolfgang Grandegger (04.06.2002)
diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c
deleted file mode 100644
index ef8bfde..0000000
--- a/board/siemens/common/fpga.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <common.h>
-
-#include "fpga.h"
-
-int  power_on_reset(void);
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-
-static int fpga_get_version(fpga_t* fpga, char* name)
-{
-    char vname[12];
-    /*
-     * Net-list string format:
-     *     "vvvvvvvvddddddddn...".
-     *     Version Date    Name
-     *     "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
-     */
-    if (strlen(name) < (16 + strlen(fpga->name)))
-	goto failure;
-    /* Check FPGA name */
-    if (strcmp(&name[16], fpga->name) != 0)
-	goto failure;
-    /* Get version number */
-    memcpy(vname, name, 8);
-    vname[8] = '\0';
-    return simple_strtoul(vname, NULL, 16);
-
- failure:
-    printf("Image name %s is invalid\n", name);
-    return -1;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static fpga_t* fpga_get(char* fpga_name)
-{
-    char name[FPGA_NAME_LEN];
-    int i;
-
-    if (strlen(fpga_name) >= FPGA_NAME_LEN)
-	goto failure;
-    for (i = 0; i < strlen(fpga_name); i++)
-	name[i] = toupper(fpga_name[i]);
-    name[i] = '\0';
-    for (i = 0; i < fpga_count; i++) {
-	if (strcmp(name, fpga_list[i].name) == 0)
-	    return &fpga_list[i];
-    }
- failure:
-    printf("FPGA: name %s is invalid\n", fpga_name);
-    return NULL;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void fpga_status (fpga_t* fpga)
-{
-    /* Check state */
-    if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
-	printf ("%s is loaded (%08lx)\n",
-		fpga->name, fpga_control(fpga, FPGA_GET_ID));
-    else
-	printf ("%s is NOT loaded\n", fpga->name);
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
-
-static int fpga_reset (fpga_t* fpga)
-{
-    int i;
-
-    /* Set PROG to low and wait til INIT goes low */
-    fpga_control(fpga, FPGA_PROG_SET_LOW);
-    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
-	udelay (100);
-	if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
-	    break;
-    }
-    if (i == FPGA_RESET_TIMEOUT)
-	goto failure;
-
-    /* Set PROG to high and wait til INIT goes high */
-    fpga_control(fpga, FPGA_PROG_SET_HIGH);
-    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
-	udelay (100);
-	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
-	    break;
-    }
-    if (i == FPGA_RESET_TIMEOUT)
-	goto failure;
-
-    return 0;
- failure:
-    return 1;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
-
-static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
-{
-    volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
-    image_header_t *hdr = (image_header_t *)addr;
-    ulong len;
-    uchar *data;
-    char msg[32];
-    int verify, i;
-
-#if defined(CONFIG_FIT)
-    if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-	puts ("Non legacy image format not supported\n");
-	return -1;
-    }
-#endif
-
-    /*
-     * Check the image header and data of the net-list
-     */
-    if (!image_check_magic (hdr)) {
-	strcpy (msg, "Bad Image Magic Number");
-	goto failure;
-    }
-
-    if (!image_check_hcrc (hdr)) {
-	strcpy (msg, "Bad Image Header CRC");
-	goto failure;
-    }
-
-    data = (uchar*)image_get_data (hdr);
-    len  = image_get_data_size (hdr);
-
-    verify = getenv_yesno ("verify");
-    if (verify) {
-	if (!image_check_dcrc (hdr)) {
-	    strcpy (msg, "Bad Image Data CRC");
-	    goto failure;
-	}
-    }
-
-    if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0)
-	return 1;
-
-    /* align length */
-    if (len & 1)
-	++len;
-
-    /*
-     * Reset FPGA and wait for completion
-     */
-    if (fpga_reset(fpga)) {
-	strcpy (msg, "Reset Timeout");
-	goto failure;
-    }
-
-    printf ("(%s)... ", image_get_name (hdr));
-    /*
-     * Copy data to FPGA
-     */
-    fpga_control (fpga, FPGA_LOAD_MODE);
-    while (len--) {
-	*fpga_addr = *data++;
-    }
-    fpga_control (fpga, FPGA_READ_MODE);
-
-    /*
-     * Wait for completion and check error status if timeout
-     */
-    for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
-	udelay (100);
-	if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
-	    break;
-    }
-    if (i == FPGA_LOAD_TIMEOUT) {
-	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
-	    strcpy(msg, "Invalid Size");
-	else
-	    strcpy(msg, "CRC Error");
-	goto failure;
-    }
-
-    printf("done\n");
-    return 0;
-
- failure:
-
-    printf("ERROR: %s\n", msg);
-    return 1;
-}
-
-#if defined(CONFIG_CMD_BSP)
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-    ulong addr = 0;
-    int i;
-    fpga_t* fpga;
-
-    if (argc < 2)
-	goto failure;
-
-    if (strncmp(argv[1], "stat", 4) == 0) {		/* status */
-	if (argc == 2) {
-	    for (i = 0; i < fpga_count; i++) {
-		fpga_status (&fpga_list[i]);
-	    }
-	}
-	else if (argc == 3) {
-	    if ((fpga = fpga_get(argv[2])) == 0)
-		goto failure;
-	    fpga_status (fpga);
-	}
-	else
-	    goto failure;
-    }
-    else if (strcmp(argv[1],"load") == 0) {		/* load */
-	if (argc == 3 && fpga_count == 1) {
-	    fpga = &fpga_list[0];
-	}
-	else if (argc == 4) {
-	    if ((fpga = fpga_get(argv[2])) == 0)
-		goto failure;
-	}
-	else
-	    goto failure;
-
-	addr = simple_strtoul(argv[argc-1], NULL, 16);
-
-	printf ("FPGA load %s: addr %08lx: ",
-		fpga->name, addr);
-	fpga_load (fpga, addr, 1);
-
-    }
-    else if (strncmp(argv[1], "rese", 4) == 0) {	/* reset */
-	if (argc == 2 && fpga_count == 1) {
-	    fpga = &fpga_list[0];
-	}
-	else if (argc == 3) {
-	    if ((fpga = fpga_get(argv[2])) == 0)
-		goto failure;
-	}
-	else
-	    goto failure;
-
-	printf ("FPGA reset %s: ", fpga->name);
-	if (fpga_reset(fpga))
-	    printf ("ERROR: Timeout\n");
-	else
-	    printf ("done\n");
-    }
-    else
-	goto failure;
-
-    return 0;
-
- failure:
-    return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
-	fpga,	4,	1,	do_fpga,
-	"access FPGA(s)",
-	"fpga status [name] - print FPGA status\n"
-	"fpga reset  [name] - reset FPGA\n"
-	"fpga load [name] addr - load FPGA configuration data"
-);
-
-#endif
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-int fpga_init (void)
-{
-    ulong addr;
-    ulong new_id, old_id = 0;
-    image_header_t *hdr;
-    fpga_t* fpga;
-    int do_load, i, j;
-    char name[16], *s;
-
-    /*
-     *  Port setup for FPGA control
-     */
-    for (i = 0; i < fpga_count; i++) {
-	fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
-    }
-
-    /*
-     * Load FPGA(s): a new net-list is loaded if the FPGA is
-     * empty, Power-on-Reset or the old one is not up-to-date
-     */
-    for (i = 0; i < fpga_count; i++) {
-	fpga = &fpga_list[i];
-	printf ("%s:  ", fpga->name);
-
-	for (j = 0; j < strlen(fpga->name); j++)
-	    name[j] = tolower(fpga->name[j]);
-	name[j] = '\0';
-	sprintf(name, "%s_addr", name);
-	addr = 0;
-	if ((s = getenv(name)) != NULL)
-	    addr = simple_strtoul(s, NULL, 16);
-
-	if (!addr) {
-	    printf ("env. variable %s undefined\n", name);
-	    return 1;
-	}
-
-	hdr = (image_header_t *)addr;
-#if defined(CONFIG_FIT)
-	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-	   puts ("Non legacy image format not supported\n");
-	   return -1;
-	}
-#endif
-
-	if ((new_id = fpga_get_version(fpga, image_get_name (hdr))) == -1)
-	    return 1;
-
-	do_load = 1;
-
-	if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
-	    old_id = fpga_control(fpga, FPGA_GET_ID);
-	    if (new_id == old_id)
-		do_load = 0;
-	}
-
-	if (do_load) {
-	    printf ("loading ");
-	    fpga_load (fpga, addr, 0);
-	} else {
-	    printf ("loaded (%08lx)\n", old_id);
-	}
-    }
-
-    return 0;
-}
diff --git a/board/siemens/common/fpga.h b/board/siemens/common/fpga.h
deleted file mode 100644
index 2de25b0..0000000
--- a/board/siemens/common/fpga.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#ifndef _FPGA_H_
-#define _FPGA_H_
-
-#define FPGA_INIT_IS_HIGH   0
-#define FPGA_INIT_SET_HIGH  1
-#define FPGA_INIT_SET_LOW   2
-#define FPGA_PROG_SET_HIGH  3
-#define FPGA_PROG_SET_LOW   4
-#define FPGA_DONE_IS_HIGH   5
-#define	FPGA_READ_MODE      6
-#define FPGA_LOAD_MODE      7
-#define FPGA_GET_ID         8
-#define FPGA_INIT_PORTS     9
-
-#define FPGA_NAME_LEN       8
-typedef struct {
-    char  name[FPGA_NAME_LEN];
-    ulong conf_base;
-    uint  init_mask;
-    uint  prog_mask;
-    uint  done_mask;
-} fpga_t;
-
-extern fpga_t fpga_list[];
-extern int    fpga_count;
-
-ulong fpga_control (fpga_t* fpga, int cmd);
-
-#endif /* _FPGA_H_ */
diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds
index 02d1980..6cf7a01 100644
--- a/board/sixnet/u-boot.lds
+++ b/board/sixnet/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds
index 9ab248a..f57f8a0 100644
--- a/board/snmc/qs850/u-boot.lds
+++ b/board/snmc/qs850/u-boot.lds
@@ -69,9 +69,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/snmc/qs860t/u-boot.lds
+++ b/board/snmc/qs860t/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds
index d0b60cf..18f962c 100644
--- a/board/spc1920/u-boot.lds
+++ b/board/spc1920/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds
index a84e7fd..f69e39d 100644
--- a/board/spd8xx/u-boot.lds
+++ b/board/spd8xx/u-boot.lds
@@ -75,9 +75,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug
index a95c47f..4155b60 100644
--- a/board/spd8xx/u-boot.lds.debug
+++ b/board/spd8xx/u-boot.lds.debug
@@ -107,9 +107,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds
index a949e4f..cdc1fda 100644
--- a/board/stx/stxxtc/u-boot.lds
+++ b/board/stx/stxxtc/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug
index a001f3f..900da64 100644
--- a/board/stx/stxxtc/u-boot.lds.debug
+++ b/board/stx/stxxtc/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds
index c65f022..1635875 100644
--- a/board/svm_sc8xx/u-boot.lds
+++ b/board/svm_sc8xx/u-boot.lds
@@ -83,9 +83,11 @@ SECTIONS
 
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/sx1/Makefile b/board/sx1/Makefile
deleted file mode 100644
index 292459f..0000000
--- a/board/sx1/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2004-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sx1.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/sx1/config.mk b/board/sx1/config.mk
deleted file mode 100644
index 441bea2..0000000
--- a/board/sx1/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
-#
-# SX1 board with OMAP1510 (ARM925T) cpu
-# see http://www.ti.com/ for more information on Texas Insturments
-#
-# SX1 has 1 bank of 256 MB SDRAM
-# Physical Address:
-# 1000'0000 to 2000'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
-#
-# we load ourself to 1108'0000
-#
-#
-
-CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/board/sx1/lowlevel_init.S b/board/sx1/lowlevel_init.S
deleted file mode 100644
index c1a811a..0000000
--- a/board/sx1/lowlevel_init.S
+++ /dev/null
@@ -1,397 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- *
- * -- Some bits of code used from rrload's head_OMAP1510.s --
- * Copyright (C) 2002 RidgeRun, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1510)
-#include <./configs/omap1510.h>
-#endif
-
-#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
-
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	 /* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/*
-	 * Configure 1510 pins functions to match our board.
-	 */
-	ldr	r0, REG_PULL_DWN_CTRL_0
-	ldr	r1, VAL_PULL_DWN_CTRL_0
-	str	r1, [r0]
-	ldr	r0, REG_PULL_DWN_CTRL_1
-	ldr	r1, VAL_PULL_DWN_CTRL_1
-	str	r1, [r0]
-	ldr	r0, REG_PULL_DWN_CTRL_2
-	ldr	r1, VAL_PULL_DWN_CTRL_2
-	str	r1, [r0]
-	ldr	r0, REG_PULL_DWN_CTRL_3
-	ldr	r1, VAL_PULL_DWN_CTRL_3
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_4
-	ldr	r1, VAL_FUNC_MUX_CTRL_4
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_5
-	ldr	r1, VAL_FUNC_MUX_CTRL_5
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_6
-	ldr	r1, VAL_FUNC_MUX_CTRL_6
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_7
-	ldr	r1, VAL_FUNC_MUX_CTRL_7
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_8
-	ldr	r1, VAL_FUNC_MUX_CTRL_8
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_9
-	ldr	r1, VAL_FUNC_MUX_CTRL_9
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_A
-	ldr	r1, VAL_FUNC_MUX_CTRL_A
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_B
-	ldr	r1, VAL_FUNC_MUX_CTRL_B
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_C
-	ldr	r1, VAL_FUNC_MUX_CTRL_C
-	str	r1, [r0]
-	ldr	r0, REG_FUNC_MUX_CTRL_D
-	ldr	r1, VAL_FUNC_MUX_CTRL_D
-	str	r1, [r0]
-	ldr	r0, REG_VOLTAGE_CTRL_0
-	ldr	r1, VAL_VOLTAGE_CTRL_0
-	str	r1, [r0]
-	ldr	r0, REG_TEST_DBG_CTRL_0
-	ldr	r1, VAL_TEST_DBG_CTRL_0
-	str	r1, [r0]
-	ldr	r0, REG_MOD_CONF_CTRL_0
-	ldr	r1, VAL_MOD_CONF_CTRL_0
-	str	r1, [r0]
-
-	/* Move to 1510 mode */
-	ldr	r0, REG_COMP_MODE_CTRL_0
-	ldr	r1, VAL_COMP_MODE_CTRL_0
-	str	r1, [r0]
-
-	/* Set up Traffic Ctlr*/
-	ldr r0, REG_TC_IMIF_PRIO
-	mov r1, #0x0
-	str r1, [r0]
-	ldr r0, REG_TC_EMIFS_PRIO
-	str r1, [r0]
-	ldr r0, REG_TC_EMIFF_PRIO
-	str r1, [r0]
-
-	ldr r0, REG_TC_EMIFS_CONFIG
-	ldr r1, [r0]
-	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
-	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
-	str r1, [r0]	    /* EMIFS GlB Configuration. (value 0x12 most likely) */
-
-	ldr r0, _GPIO_PIN_CONTROL_REG
-	mov r1,#0
-	orr r1, r1, #0x0001 /* M_PCM_SYNC */
-	orr r1, r1, #0x4000 /* IPC_ACTIVE */
-	strh r1,[r0]
-
-	ldr r0, _GPIO_DIR_CONTROL_REG
-	mov r1,#0
-	bic r1, r1, #0x0001 /* M_PCM_SYNC */
-	bic r1, r1, #0x4000 /* IPC_ACTIVE */
-	strh r1,[r0]
-
-	ldr r0, _GPIO_DATA_OUTPUT_REG
-	mov r1,#0
-	bic r1, r1, #0x0001 /* M_PCM_SYNC */
-	orr r1, r1, #0x4000 /* IPC_ACTIVE */
-	strh r1,[r0]
-
-	/* Setup some clock domains */
-	ldr r1, =OMAP1510_CLKS
-	ldr r0, REG_ARM_IDLECT2
-	strh r1, [r0]  /* CLKM, Clock domain control. */
-
-	mov r1, #0x01  /* PER_EN bit */
-	ldr r0, REG_ARM_RSTCT2
-	strh r1, [r0]  /* CLKM; Peripheral reset. */
-
-	/* Set CLKM to Sync-Scalable  */
-	/* I supposidly need to enable the dsp clock before switching */
-	mov r1, #0x1000
-	ldr r0, REG_ARM_SYSST
-	strh r1, [r0]
-	mov r0, #0x400
-1:
-	subs r0, r0, #0x1   /* wait for any bubbles to finish */
-	bne 1b
-
-	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
-	ldr r0, REG_ARM_CKCTL
-	strh r1, [r0]
-
-	/* setup DPLL 1 */
-	ldr r1, VAL_DPLL1_CTL
-	ldr r0, REG_DPLL1_CTL
-	strh r1, [r0]
-	ands r1, r1, #0x10  /* Check if PLL is enabled. */
-	beq lock_end	    /* Do not look for lock if BYPASS selected */
-2:
-	ldrh r1, [r0]
-	ands r1, r1, #0x01  /* Check the LOCK bit. */
-	beq 2b		    /* ...loop until bit goes hi. */
-lock_end:
-
-	/* Set memory timings corresponding to the new clock speed */
-
-	/* Check execution location to determine current execution location
-	 * and branch to appropriate initialization code.
-	 */
-	mov r0, #0x10000000		    /* Load physical SDRAM base. */
-	mov r1, pc			    /* Get current execution location. */
-	cmp r1, r0			    /* Compare. */
-	bge skip_sdram			    /* Skip over EMIF-fast initialization if running from SDRAM. */
-
-	/*
-	 * Delay for SDRAM initialization.
-	 */
-	mov r3, #0x1800			       /* value should be checked */
-3:
-	subs r3, r3, #0x1		      /* Decrement count */
-	bne 3b
-
-	/*
-	 * Set SDRAM control values. Disable refresh before MRS command.
-	 */
-	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
-	bic r3, r0, #0xC		    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
-	orr r3, r3, #0x8000000		    /* (BIT27) Disable CLK when Power down or Self-Refresh */
-	orr r3, r3, #0x4000000		    /* BIT26 Power Down Enable */
-	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-	str r3, [r2]			    /* Store the passed value with AR disabled. */
-
-	ldr r1, VAL_TC_EMIFF_MRS	    /* get MRS value */
-	ldr r2, REG_TC_EMIFF_MRS	    /* Point to MRS register. */
-	str r1, [r2]			    /* Store the passed value.*/
-
-	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-	str r0, [r2]			    /* Store the passed value. */
-
-	/*
-	 * Delay for SDRAM initialization.
-	 */
-	mov r3, #0x1800
-4:
-	subs r3, r3, #1			    /* Decrement count. */
-	bne 4b
-
-skip_sdram:
-
-	/* slow interface */
-	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
-	ldr r0, REG_TC_EMIFS_CS0_CONFIG
-	str r1, [r0] /* Chip Select 0 */
-	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
-	ldr r0, REG_TC_EMIFS_CS1_CONFIG
-	str r1, [r0] /* Chip Select 1 */
-	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
-	ldr r0, REG_TC_EMIFS_CS2_CONFIG
-	str r1, [r0] /* Chip Select 2 */
-	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
-	ldr r0, REG_TC_EMIFS_CS3_CONFIG
-	str r1, [r0] /* Chip Select 3 */
-
-	/* back to arch calling code */
-	mov	pc, lr
-
-/* the literal pools origin */
-	.ltorg
-
-/* OMAP configuration registers */
-REG_FUNC_MUX_CTRL_0:		/* 32 bits */
-	.word 0xfffe1000
-REG_FUNC_MUX_CTRL_1:		/* 32 bits */
-	.word 0xfffe1004
-REG_FUNC_MUX_CTRL_2:		/* 32 bits */
-	.word 0xfffe1008
-REG_COMP_MODE_CTRL_0:		/* 32 bits */
-	.word 0xfffe100c
-REG_FUNC_MUX_CTRL_3:		/* 32 bits */
-	.word 0xfffe1010
-REG_FUNC_MUX_CTRL_4:		/* 32 bits */
-	.word 0xfffe1014
-REG_FUNC_MUX_CTRL_5:		/* 32 bits */
-	.word 0xfffe1018
-REG_FUNC_MUX_CTRL_6:		/* 32 bits */
-	.word 0xfffe101c
-REG_FUNC_MUX_CTRL_7:		/* 32 bits */
-	.word 0xfffe1020
-REG_FUNC_MUX_CTRL_8:		/* 32 bits */
-	.word 0xfffe1024
-REG_FUNC_MUX_CTRL_9:		/* 32 bits */
-	.word 0xfffe1028
-REG_FUNC_MUX_CTRL_A:		/* 32 bits */
-	.word 0xfffe102C
-REG_FUNC_MUX_CTRL_B:		/* 32 bits */
-	.word 0xfffe1030
-REG_FUNC_MUX_CTRL_C:		/* 32 bits */
-	.word 0xfffe1034
-REG_FUNC_MUX_CTRL_D:		/* 32 bits */
-	.word 0xfffe1038
-REG_PULL_DWN_CTRL_0:		/* 32 bits */
-	.word 0xfffe1040
-REG_PULL_DWN_CTRL_1:		/* 32 bits */
-	.word 0xfffe1044
-REG_PULL_DWN_CTRL_2:		/* 32 bits */
-	.word 0xfffe1048
-REG_PULL_DWN_CTRL_3:		/* 32 bits */
-	.word 0xfffe104c
-REG_VOLTAGE_CTRL_0:		/* 32 bits */
-	.word 0xfffe1060
-REG_TEST_DBG_CTRL_0:		/* 32 bits */
-	.word 0xfffe1070
-REG_MOD_CONF_CTRL_0:		/* 32 bits */
-	.word 0xfffe1080
-REG_TC_IMIF_PRIO:		/* 32 bits */
-	.word 0xfffecc00
-REG_TC_EMIFS_PRIO:		/* 32 bits */
-	.word 0xfffecc04
-REG_TC_EMIFF_PRIO:		/* 32 bits */
-	.word 0xfffecc08
-REG_TC_EMIFS_CONFIG:		/* 32 bits */
-	.word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
-	.word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
-	.word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
-	.word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
-	.word 0xfffecc1c
-REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
-	.word 0xfffecc20
-REG_TC_EMIFF_MRS:		/* 32 bits */
-	.word 0xfffecc24
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:			/* 16 bits */
-	.word 0xfffece00
-REG_ARM_IDLECT2:		/* 16 bits */
-	.word 0xfffece08
-REG_ARM_RSTCT2:			/* 16 bits */
-	.word 0xfffece14
-REG_ARM_SYSST:			/* 16 bits */
-	.word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:			/* 16 bits */
-	.word 0xfffecf00
-/* identification code register */
-REG_IDCODE:			/* 32 bits */
-	.word 0xfffed404
-
-/* SX1 specific */
-_GPIO_PIN_CONTROL_REG:
-	.word GPIO_PIN_CONTROL_REG
-_GPIO_DIR_CONTROL_REG:
-	.word GPIO_DIR_CONTROL_REG
-_GPIO_DATA_OUTPUT_REG:
-	.word GPIO_DATA_OUTPUT_REG
-
-VAL_COMP_MODE_CTRL_0:
-	.word 0x0000eaef
-VAL_FUNC_MUX_CTRL_4:
-	.word 0x00000000
-VAL_FUNC_MUX_CTRL_5:
-	.word 0x00000000
-VAL_FUNC_MUX_CTRL_6:
-	.word 0x00000001
-VAL_FUNC_MUX_CTRL_7:
-	.word 0x00001000
-VAL_FUNC_MUX_CTRL_8:
-	.word 0x00001240       /*[Knoller]  Value of Symbian Image Wing B2*/
-VAL_FUNC_MUX_CTRL_9:
-	.word 0x00201008
-VAL_FUNC_MUX_CTRL_A:
-	.word 0x00001000
-VAL_FUNC_MUX_CTRL_B:
-	.word 0x00000000
-VAL_FUNC_MUX_CTRL_C:
-	.word 0x09008001       /*[Knoller]  Value of Symbian Image Wing B2*/
-VAL_FUNC_MUX_CTRL_D:
-	.word 0x00000000
-VAL_PULL_DWN_CTRL_0:
-	.word 0xfffeffff
-VAL_PULL_DWN_CTRL_1:
-	.word 0xd1ffffec
-VAL_PULL_DWN_CTRL_2:
-	.word 0xffa80c5b
-VAL_PULL_DWN_CTRL_3:
-	.word 0xffffc0fe
-VAL_VOLTAGE_CTRL_0:
-	.word 0x00000007
-VAL_TEST_DBG_CTRL_0:
-	/* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
-	 * says to write a 7.  Don't know what the right thing is to do, so
-	 * I'm leaving it at 7 since that's what was already here.
-	 */
-	.word 0x00000007
-VAL_MOD_CONF_CTRL_0:
-	.word 0x0da20000       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_ARM_CKCTL:
-	.word 0x010D
-
-VAL_DPLL1_CTL:
-	.word 0x3A33   /*[Hertle] Value of Symbian Image*/
-
-VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
-	.word 0x00001149
-
-VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
-	.word 0x00004158
-
-VAL_TC_EMIFS_CS0_CONFIG:
-	.word 0x00213090       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_TC_EMIFS_CS1_CONFIG:
-	.word 0x00215070       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_TC_EMIFS_CS2_CONFIG:
-	.word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_TC_EMIFS_CS3_CONFIG:
-	.word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-VAL_TC_EMIFF_SDRAM_CONFIG:
-	.word 0x0105f0b4       /*[Knoller]  Value of Symbian Image Wing B2*/
-
-
-VAL_TC_EMIFF_MRS:
-	.word 0x00000027       /*[Knoller]  Value of Symbian Image Wing B2*/
diff --git a/board/sx1/sx1.c b/board/sx1/sx1.c
deleted file mode 100644
index aaef76e..0000000
--- a/board/sx1/sx1.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void flash__init (void);
-static void ether__init (void);
-
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-			  "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* arch number of SX1 Board */
-	gd->bd->bi_arch_number = MACH_TYPE_SX1;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x10000100;
-
-/* kk - this speeds up your boot a quite a bit.	 However to make it
- *  work, you need make sure your kernel startup flush bug is fixed.
- *  ... rkw ...
- */
-	icache_enable ();
-
-	flash__init ();
-	ether__init ();
-	return 0;
-}
-
-
-int misc_init_r (void)
-{
-	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
-	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
-
-	/* setup gpio direction to match board (no floats!) */
-	/**gdir = 0xCFF9; */
-	/**mdir = 0x103F; */
-
-	return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-static void flash__init (void)
-{
-#define CS0_CHIP_SELECT_REG 0xfffecc10
-#define CS3_CHIP_SELECT_REG 0xfffecc1c
-#define EMIFS_GlB_Config_REG 0xfffecc0c
-
-	unsigned int regval;
-
-	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
-	regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
-	if (regval & 0x0002) {
-		regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
-		/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
-		/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
-		/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
-	}
-	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
-}
-
-
-/******************************
- Routine:
- Description:
-******************************/
-static void ether__init (void)
-{
-#define ETH_CONTROL_REG 0x0800000b
-	/* take the Ethernet controller out of reset and wait
-	 * for the EEPROM load to complete.
-	 */
-	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
-	udelay (3);
-}
-
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index ecb9b6c..9622a81 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -45,6 +45,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define BUZZER		140
 #define SPEAKER		141
+#define USB1_PWR	127
+#define USB2_PWR	149
 
 #ifndef CONFIG_FPGA
 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
@@ -247,6 +249,12 @@ int board_init(void)
 	gpio_direction_output(BUZZER, 0);
 	gpio_direction_output(SPEAKER, 0);
 
+	/* Activate USB power */
+	gpio_request(USB1_PWR, "USB1_PWR");
+	gpio_request(USB2_PWR, "USB2_PWR");
+	gpio_direction_output(USB1_PWR, 1);
+	gpio_direction_output(USB2_PWR, 1);
+
 	return 0;
 }
 
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
index ca50eef..67a87a1 100644
--- a/board/ti/am335x/Makefile
+++ b/board/ti/am335x/Makefile
@@ -22,6 +22,7 @@ ifdef CONFIG_SPL_BUILD
 COBJS	:= mux.o
 endif
 
+COBJS	+= board.o
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
new file mode 100644
index 0000000..b56a801
--- /dev/null
+++ b/board/ti/am335x/board.c
@@ -0,0 +1,418 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* MII mode defines */
+#define MII_MODE_ENABLE		0x0
+#define RGMII_MODE_ENABLE	0xA
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN		7
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static struct am335x_baseboard_id __attribute__((section (".data"))) header;
+
+static inline int board_is_bone(void)
+{
+	return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
+}
+
+static inline int board_is_bone_lt(void)
+{
+	return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_sk(void)
+{
+	return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
+}
+
+static inline int board_is_idk(void)
+{
+	return !strncmp(header.config, "SKU#02", 6);
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		puts("Could not probe the EEPROM; something fundamentally "
+			"wrong on the I2C bus.\n");
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+							sizeof(header))) {
+		puts("Could not read the EEPROM; something fundamentally"
+			" wrong on the I2C bus.\n");
+		return -EIO;
+	}
+
+	if (header.magic != 0xEE3355AA) {
+		/*
+		 * read the eeprom using i2c again,
+		 * but use only a 1 byte address
+		 */
+		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
+					(uchar *)&header, sizeof(header))) {
+			puts("Could not read the EEPROM; something "
+				"fundamentally wrong on the I2C bus.\n");
+			return -EIO;
+		}
+
+		if (header.magic != 0xEE3355AA) {
+			printf("Incorrect magic number (0x%x) in EEPROM\n",
+					header.magic);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+static void rtc32k_enable(void)
+{
+	struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(0x83e70b13, &rtc->kick0r);
+	writel(0x95a4f1e0, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static const struct ddr_data ddr2_data = {
+	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
+			  (MT47H128M16RT25E_RD_DQS<<20) |
+			  (MT47H128M16RT25E_RD_DQS<<10) |
+			  (MT47H128M16RT25E_RD_DQS<<0)),
+	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
+			  (MT47H128M16RT25E_WR_DQS<<20) |
+			  (MT47H128M16RT25E_WR_DQS<<10) |
+			  (MT47H128M16RT25E_WR_DQS<<0)),
+	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
+			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
+			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
+			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
+	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
+			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
+			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
+			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
+	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
+			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
+			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
+			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
+	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
+			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
+			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
+			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+	.cmd0csratio = MT47H128M16RT25E_RATIO,
+	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
+	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT47H128M16RT25E_RATIO,
+	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
+	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT47H128M16RT25E_RATIO,
+	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
+	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41J128MJT125_RD_DQS,
+	.datawdsratio0 = MT41J128MJT125_WR_DQS,
+	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
+	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41J128MJT125_RATIO,
+	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41J128MJT125_RATIO,
+	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41J128MJT125_RATIO,
+	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
+	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
+	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
+	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
+	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
+	.zq_config = MT41J128MJT125_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
+};
+#endif
+
+/*
+ * early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+	/* WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+
+#ifdef CONFIG_SPL_BUILD
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
+	/* UART softreset */
+	u32 regVal;
+
+#ifdef CONFIG_SERIAL1
+	enable_uart0_pin_mux();
+#endif /* CONFIG_SERIAL1 */
+#ifdef CONFIG_SERIAL2
+	enable_uart1_pin_mux();
+#endif /* CONFIG_SERIAL2 */
+#ifdef CONFIG_SERIAL3
+	enable_uart2_pin_mux();
+#endif /* CONFIG_SERIAL3 */
+#ifdef CONFIG_SERIAL4
+	enable_uart3_pin_mux();
+#endif /* CONFIG_SERIAL4 */
+#ifdef CONFIG_SERIAL5
+	enable_uart4_pin_mux();
+#endif /* CONFIG_SERIAL5 */
+#ifdef CONFIG_SERIAL6
+	enable_uart5_pin_mux();
+#endif /* CONFIG_SERIAL6 */
+
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_RESET;
+	writel(regVal, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_SMART_IDLE_EN;
+	writel(regVal, &uart_base->uartsyscfg);
+
+	gd = &gdata;
+
+	preloader_console_init();
+
+	/* Initalize the board header */
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+
+	enable_board_pin_mux(&header);
+	if (board_is_evm_sk()) {
+		/*
+		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
+		 * This is safe enough to do on older revs.
+		 */
+		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+	}
+
+	if (board_is_evm_sk() || board_is_bone_lt())
+		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+	else
+		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
+			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
+#endif
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+
+	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	char safe_string[HDR_NAME_LEN + 1];
+
+	/* Now set variables based on the header. */
+	strncpy(safe_string, (char *)header.name, sizeof(header.name));
+	safe_string[sizeof(header.name)] = 0;
+	setenv("board_name", safe_string);
+
+	strncpy(safe_string, (char *)header.version, sizeof(header.version));
+	safe_string[sizeof(header.version)] = 0;
+	setenv("board_rev", safe_string);
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_id		= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_id		= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= AM335X_CPSW_MDIO_BASE,
+	.cpsw_base		= AM335X_CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		debug("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ether_addr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			return -1;
+	}
+
+	if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
+		writel(MII_MODE_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+				PHY_INTERFACE_MODE_MII;
+	} else {
+		writel(RGMII_MODE_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+				PHY_INTERFACE_MODE_RGMII;
+	}
+
+	return cpsw_register(&cpsw_data);
+}
+#endif
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
new file mode 100644
index 0000000..48e112e
--- /dev/null
+++ b/board/ti/am335x/board.h
@@ -0,0 +1,54 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * TI AM335x parts define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR	3
+#define HDR_ETH_ALEN		6
+#define HDR_NAME_LEN		8
+
+struct am335x_baseboard_id {
+	unsigned int  magic;
+	char name[HDR_NAME_LEN];
+	char version[4];
+	char serial[12];
+	char config[32];
+	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(struct am335x_baseboard_id *header);
+#endif
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 80becd5..8437ef5 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -16,246 +16,44 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
 #include <asm/io.h>
 #include <i2c.h>
+#include "board.h"
 
-#define MUX_CFG(value, offset)	\
-	__raw_writel(value, (CTRL_BASE + offset));
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
 
-/* PAD Control Fields */
-#define SLEWCTRL	(0x1 << 6)
-#define RXACTIVE	(0x1 << 5)
-#define PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
-#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
-#define MODE(val)	val	/* used for Readability */
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
+	{-1},
+};
 
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-	int gpmc_ad0;
-	int gpmc_ad1;
-	int gpmc_ad2;
-	int gpmc_ad3;
-	int gpmc_ad4;
-	int gpmc_ad5;
-	int gpmc_ad6;
-	int gpmc_ad7;
-	int gpmc_ad8;
-	int gpmc_ad9;
-	int gpmc_ad10;
-	int gpmc_ad11;
-	int gpmc_ad12;
-	int gpmc_ad13;
-	int gpmc_ad14;
-	int gpmc_ad15;
-	int gpmc_a0;
-	int gpmc_a1;
-	int gpmc_a2;
-	int gpmc_a3;
-	int gpmc_a4;
-	int gpmc_a5;
-	int gpmc_a6;
-	int gpmc_a7;
-	int gpmc_a8;
-	int gpmc_a9;
-	int gpmc_a10;
-	int gpmc_a11;
-	int gpmc_wait0;
-	int gpmc_wpn;
-	int gpmc_be1n;
-	int gpmc_csn0;
-	int gpmc_csn1;
-	int gpmc_csn2;
-	int gpmc_csn3;
-	int gpmc_clk;
-	int gpmc_advn_ale;
-	int gpmc_oen_ren;
-	int gpmc_wen;
-	int gpmc_be0n_cle;
-	int lcd_data0;
-	int lcd_data1;
-	int lcd_data2;
-	int lcd_data3;
-	int lcd_data4;
-	int lcd_data5;
-	int lcd_data6;
-	int lcd_data7;
-	int lcd_data8;
-	int lcd_data9;
-	int lcd_data10;
-	int lcd_data11;
-	int lcd_data12;
-	int lcd_data13;
-	int lcd_data14;
-	int lcd_data15;
-	int lcd_vsync;
-	int lcd_hsync;
-	int lcd_pclk;
-	int lcd_ac_bias_en;
-	int mmc0_dat3;
-	int mmc0_dat2;
-	int mmc0_dat1;
-	int mmc0_dat0;
-	int mmc0_clk;
-	int mmc0_cmd;
-	int mii1_col;
-	int mii1_crs;
-	int mii1_rxerr;
-	int mii1_txen;
-	int mii1_rxdv;
-	int mii1_txd3;
-	int mii1_txd2;
-	int mii1_txd1;
-	int mii1_txd0;
-	int mii1_txclk;
-	int mii1_rxclk;
-	int mii1_rxd3;
-	int mii1_rxd2;
-	int mii1_rxd1;
-	int mii1_rxd0;
-	int rmii1_refclk;
-	int mdio_data;
-	int mdio_clk;
-	int spi0_sclk;
-	int spi0_d0;
-	int spi0_d1;
-	int spi0_cs0;
-	int spi0_cs1;
-	int ecap0_in_pwm0_out;
-	int uart0_ctsn;
-	int uart0_rtsn;
-	int uart0_rxd;
-	int uart0_txd;
-	int uart1_ctsn;
-	int uart1_rtsn;
-	int uart1_rxd;
-	int uart1_txd;
-	int i2c0_sda;
-	int i2c0_scl;
-	int mcasp0_aclkx;
-	int mcasp0_fsx;
-	int mcasp0_axr0;
-	int mcasp0_ahclkr;
-	int mcasp0_aclkr;
-	int mcasp0_fsr;
-	int mcasp0_axr1;
-	int mcasp0_ahclkx;
-	int xdma_event_intr0;
-	int xdma_event_intr1;
-	int nresetin_out;
-	int porz;
-	int nnmi;
-	int osc0_in;
-	int osc0_out;
-	int rsvd1;
-	int tms;
-	int tdi;
-	int tdo;
-	int tck;
-	int ntrst;
-	int emu0;
-	int emu1;
-	int osc1_in;
-	int osc1_out;
-	int pmic_power_en;
-	int rtc_porz;
-	int rsvd2;
-	int ext_wakeup;
-	int enz_kaldo_1p8v;
-	int usb0_dm;
-	int usb0_dp;
-	int usb0_ce;
-	int usb0_id;
-	int usb0_vbus;
-	int usb0_drvvbus;
-	int usb1_dm;
-	int usb1_dp;
-	int usb1_ce;
-	int usb1_id;
-	int usb1_vbus;
-	int usb1_drvvbus;
-	int ddr_resetn;
-	int ddr_csn0;
-	int ddr_cke;
-	int ddr_ck;
-	int ddr_nck;
-	int ddr_casn;
-	int ddr_rasn;
-	int ddr_wen;
-	int ddr_ba0;
-	int ddr_ba1;
-	int ddr_ba2;
-	int ddr_a0;
-	int ddr_a1;
-	int ddr_a2;
-	int ddr_a3;
-	int ddr_a4;
-	int ddr_a5;
-	int ddr_a6;
-	int ddr_a7;
-	int ddr_a8;
-	int ddr_a9;
-	int ddr_a10;
-	int ddr_a11;
-	int ddr_a12;
-	int ddr_a13;
-	int ddr_a14;
-	int ddr_a15;
-	int ddr_odt;
-	int ddr_d0;
-	int ddr_d1;
-	int ddr_d2;
-	int ddr_d3;
-	int ddr_d4;
-	int ddr_d5;
-	int ddr_d6;
-	int ddr_d7;
-	int ddr_d8;
-	int ddr_d9;
-	int ddr_d10;
-	int ddr_d11;
-	int ddr_d12;
-	int ddr_d13;
-	int ddr_d14;
-	int ddr_d15;
-	int ddr_dqm0;
-	int ddr_dqm1;
-	int ddr_dqs0;
-	int ddr_dqsn0;
-	int ddr_dqs1;
-	int ddr_dqsn1;
-	int ddr_vref;
-	int ddr_vtp;
-	int ddr_strben0;
-	int ddr_strben1;
-	int ain7;
-	int ain6;
-	int ain5;
-	int ain4;
-	int ain3;
-	int ain2;
-	int ain1;
-	int ain0;
-	int vrefp;
-	int vrefn;
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
 };
 
-struct module_pin_mux {
-	short reg_offset;
-	unsigned char val;
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
 };
 
-/* Pad control register offset */
-#define PAD_CTRL_BASE	0x800
-#define OFFSET(x)	(unsigned int) (&((struct pad_signals *) \
-				(PAD_CTRL_BASE))->x)
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
 
-static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
 	{-1},
 };
 
@@ -271,6 +69,17 @@ static struct module_pin_mux mmc0_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
+	{-1},
+};
+
 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
@@ -362,25 +171,35 @@ static struct module_pin_mux mii1_pin_mux[] = {
 	{-1},
 };
 
-/*
- * Configure the pin mux for the module
- */
-static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+void enable_uart0_pin_mux(void)
 {
-	int i;
+	configure_module_pin_mux(uart0_pin_mux);
+}
 
-	if (!mod_pin_mux)
-		return;
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
 
-	for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
-		MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
 }
 
-void enable_uart0_pin_mux(void)
+void enable_uart3_pin_mux(void)
 {
-	configure_module_pin_mux(uart0_pin_mux);
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
 }
 
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
 
 void enable_i2c0_pin_mux(void)
 {
@@ -442,12 +261,27 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
 			configure_module_pin_mux(mmc1_pin_mux);
 			configure_module_pin_mux(spi0_pin_mux);
 		}
+	} else if (!strncmp(header->config, "SKU#02", 6)) {
+		/*
+		 * Industrial Motor Control (IDK)
+		 * note: IDK console is on UART3 by default.
+		 *       So u-boot mus be build with CONFIG_SERIAL4 and
+		 *       CONFIG_CONS_INDEX=4
+		 */
+		configure_module_pin_mux(mii1_pin_mux);
+		configure_module_pin_mux(mmc0_no_cd_pin_mux);
 	} else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
 		/* Starter Kit EVM */
 		configure_module_pin_mux(i2c1_pin_mux);
 		configure_module_pin_mux(gpio0_7_pin_mux);
 		configure_module_pin_mux(rgmii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux_sk_evm);
+	} else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) {
+		/* Beaglebone LT pinmux */
+		configure_module_pin_mux(i2c1_pin_mux);
+		configure_module_pin_mux(mii1_pin_mux);
+		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(mmc1_pin_mux);
 	} else {
 		puts("Unknown board, cannot configure pinmux.");
 		hang();
diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c
index a3983e3..188e4ac 100644
--- a/board/ti/omap2420h4/omap2420h4.c
+++ b/board/ti/omap2420h4/omap2420h4.c
@@ -153,7 +153,7 @@ void wait_for_command_complete(unsigned int wd_base)
  ******************************************************************/
 void ether_init (void)
 {
-#ifdef CONFIG_DRIVER_LAN91C96
+#ifdef CONFIG_LAN91C96
 	int cnt = 20;
 
 	__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20-common/colibri_t20-common.c
new file mode 100644
index 0000000..6d5e47d
--- /dev/null
+++ b/board/toradex/colibri_t20-common/colibri_t20-common.c
@@ -0,0 +1,44 @@
+/*
+ *  Copyright (C) 2012 Lucas Stach
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+
+#include "colibri_t20-common.h"
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void colibri_t20_common_pin_mux_usb(void)
+{
+	/* module internal USB bus to connect ethernet chipset */
+	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+	/* ULPI reference clock output */
+	pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PINGRP_CDEV2);
+	/* PHY reset GPIO */
+	pinmux_tristate_disable(PINGRP_UAC);
+	/* VBus GPIO */
+	pinmux_tristate_disable(PINGRP_DTE);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+}
+#endif
diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.h b/board/toradex/colibri_t20-common/colibri_t20-common.h
new file mode 100644
index 0000000..76dc860
--- /dev/null
+++ b/board/toradex/colibri_t20-common/colibri_t20-common.h
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 2012 Lucas Stach
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+void colibri_t20_common_pin_mux_usb(void);
diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile
new file mode 100644
index 0000000..c138729
--- /dev/null
+++ b/board/toradex/colibri_t20_iris/Makefile
@@ -0,0 +1,40 @@
+#
+#  (C) Copyright 2012 Lucas Stach
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#
+
+include $(TOPDIR)/config.mk
+
+$(shell mkdir -p $(obj)../../nvidia/common)
+$(shell mkdir -p $(obj)../colibri_t20-common)
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ../../nvidia/common/board.o
+COBJS	+= ../colibri_t20-common/colibri_t20-common.o
+COBJS	+= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
new file mode 100644
index 0000000..e40a986
--- /dev/null
+++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
@@ -0,0 +1,46 @@
+/*
+ *  Copyright (C) 2012 Lucas Stach
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/mmc.h>
+
+#include "../colibri_t20-common/colibri_t20-common.h"
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+	colibri_t20_common_pin_mux_usb();
+
+	/* USB 1 aka Tegra USB port 3 VBus*/
+	pinmux_tristate_disable(PINGRP_SPIG);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_MMC
+int board_mmc_init(bd_t *bd)
+{
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+	pinmux_tristate_disable(PINGRP_GMB);
+
+	tegra_mmc_init(0, 4, -1, GPIO_PC7);
+
+	return 0;
+}
+#endif
diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts
new file mode 100644
index 0000000..c29b43a
--- /dev/null
+++ b/board/toradex/dts/tegra20-colibri_t20_iris.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "Toradex Colibri T20";
+	compatible = "toradex,t20", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
+		usb2 = "/usb@c5004000";
+	};
+
+	usb@c5000000 {
+		dr_mode = "otg";
+	};
+
+	usb@c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */
+		nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */
+	};
+
+	usb@c5008000 {
+		nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */
+	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */
+		nvidia,width = <8>;
+		nvidia,timing = <15 100 25 80 25 10 15 10 100>;
+
+		nand@0 {
+			reg = <0>;
+			compatible = "nand-flash";
+		};
+	};
+};
diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
index e905c26..e1e1ccd 100644
--- a/board/tqc/tqm8xx/u-boot.lds
+++ b/board/tqc/tqm8xx/u-boot.lds
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2012
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -41,8 +41,6 @@ SECTIONS
     drivers/net/libnet.o		(.text*)
     drivers/pcmcia/libpcmcia.o		(.text.pcmcia_on)
     drivers/pcmcia/libpcmcia.o		(.text.pcmcia_hardware_enable)
-    drivers/rtc/librtc.o		(.text*)
-    drivers/misc/libmisc.o		(.text*)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o	(.ppcenv*)
@@ -81,9 +79,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 871e052..c3dee84 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -34,6 +34,7 @@
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
 #include <netdev.h>
 #include <asm/io.h>
 
@@ -152,3 +153,11 @@ int board_eth_init(bd_t *bis)
 	return dm9000_initialize(bis);
 }
 #endif
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds
index e62d53d..fd2d72e 100644
--- a/board/v37/u-boot.lds
+++ b/board/v37/u-boot.lds
@@ -66,9 +66,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index 1958c2f..20161a4 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -57,6 +57,10 @@ SECTIONS
 		*(.data)
 	}
 
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
+
 	. = ALIGN(4);
 
 	.rel.dyn : {
diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug
index 1c67b30..2ce5a9a 100644
--- a/board/w7o/u-boot.lds.debug
+++ b/board/w7o/u-boot.lds.debug
@@ -106,9 +106,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
diff --git a/board/westel/amx860/Makefile b/board/westel/amx860/Makefile
deleted file mode 100644
index 12e4aa6..0000000
--- a/board/westel/amx860/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c
deleted file mode 100644
index 91dcc0d..0000000
--- a/board/westel/amx860/amx860.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-const uint edo_60ns[] =
-{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
-  0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
-  0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08,
-  0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48,
-  0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_,
-  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
-  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
-  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
-  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
-  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	puts ("Board: AMX860\n");
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-
-	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	/* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */
-
-	upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
-
-#ifndef CONFIG_AMX_RAM_EXT
-	memctl->memc_mptpr = 0x0400; /* divide by 16 */
-#else
-	memctl->memc_mptpr = 0x0200;
-#endif
-
-	memctl->memc_mamr = 0x30a21114;
-	memctl->memc_or2 = 0xffc00800;
-#ifndef CONFIG_AMX_RAM_EXT
-	memctl->memc_br2 = 0x81;
-
-	return (4 << 20);
-#else
-	memctl->memc_or1 = 0xff000800;
-	memctl->memc_br1 = 0x00000081;
-	memctl->memc_br2 = 0x01000081;
-
-	return (20 << 20);
-#endif
-}
diff --git a/board/westel/amx860/flash.c b/board/westel/amx860/flash.c
deleted file mode 100644
index fe8bce4..0000000
--- a/board/westel/amx860/flash.c
+++ /dev/null
@@ -1,637 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0, size_b1;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-#if defined(FLASH_BASE1_PRELIM) && (FLASH_BASE1_PRELIM != 0)
-	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
-
-	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
-	if (size_b1 > size_b0) {
-		printf ("## ERROR: "
-			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-			size_b1, size_b1<<20,
-			size_b0, size_b0<<20
-		);
-		flash_info[0].flash_id	= FLASH_UNKNOWN;
-		flash_info[1].flash_id	= FLASH_UNKNOWN;
-		flash_info[0].sector_count	= -1;
-		flash_info[1].sector_count	= -1;
-		flash_info[0].size		= 0;
-		flash_info[1].size		= 0;
-		return (0);
-	}
-#else
-	size_b1 = 0;
-#endif	/* FLASH_BASE1_PRELIM */
-
-	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	DEBUGF ("## Before remap: "
-		"BR0: 0x%08x    OR0: 0x%08x    "
-		"BR1: 0x%08x    OR1: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0,
-		memctl->memc_br1, memctl->memc_or1);
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0);
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-		      &flash_info[0]);
-#endif
-
-	if (size_b1) {
-		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK);
-		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
-				   BR_MS_GPCM | BR_V;
-
-		DEBUGF("## BR1: 0x%08x    OR1: 0x%08x\n",
-			memctl->memc_br1, memctl->memc_or1);
-
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
-					  &flash_info[1]);
-
-		flash_info[1].size = size_b1;
-
-		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_SYS_MONITOR_BASE,
-			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[1]);
-# endif
-
-# ifdef CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-			      &flash_info[1]);
-#endif
-	} else {
-#ifndef CONFIG_AMX_RAM_EXT
-		memctl->memc_br1 = 0;		/* invalidate bank */
-		memctl->memc_or1 = 0;		/* invalidate bank */
-#endif
-
-		DEBUGF("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
-			memctl->memc_br1, memctl->memc_or1);
-
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-		flash_info[1].size = 0;
-	}
-
-	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-		/* set sector offsets for uniform sector type	*/
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00040000);
-		}
-	} else if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
-				break;
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
-	switch (value) {
-	case AMD_ID_F040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds
deleted file mode 100644
index 3470b43..0000000
--- a/board/westel/amx860/u-boot.lds
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    net/libnet.o			(.text*)
-    board/westel/amx860/libamx860.o	(.text*)
-    *(.text.*printf)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug
deleted file mode 100644
index 91d3e67..0000000
--- a/board/westel/amx860/u-boot.lds.debug
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-    arch/powerpc/lib/extable.o	(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug
index e2e66ae..c4e5706 100644
--- a/board/xes/xpedite1000/u-boot.lds.debug
+++ b/board/xes/xpedite1000/u-boot.lds.debug
@@ -111,9 +111,11 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   __start___ex_table = .;
author	Stefano Babic <sbabic@denx.de>	2012-11-10 08:05:54 +0100
committer	Stefano Babic <sbabic@denx.de>	2012-11-10 08:05:54 +0100
commit	3e4d27b06d7484040355e22eec2cbce7335d6dab (patch)
tree	9672a2bb2e4ce0edc0ab776ddf0e2ca8e39a5f62 /board
parent	bad05afe083eec0467220de21683443292c5012e (diff)
parent	59852d03867108217fe88e3bfc3e1e9cedfe63c5 (diff)
download	u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.zip u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.gz u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.bz2