diff options
| author | Tom Rini <trini@ti.com> | 2013-03-18 12:31:00 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-18 14:37:18 -0400 |
| commit | 0ce033d2582129243aca10d3072a221386bbba44 (patch) | |
| tree | 6e50a3f4eed22007549dc740d0fa647a6c8cec5b /board | |
| parent | b5bec88434adb52413f1bc33fa63d7642cb8fd35 (diff) | |
| parent | b27673ccbd3d5435319b5c09c3e7061f559f925d (diff) | |
| download | u-boot-imx-0ce033d2582129243aca10d3072a221386bbba44.zip u-boot-imx-0ce033d2582129243aca10d3072a221386bbba44.tar.gz u-boot-imx-0ce033d2582129243aca10d3072a221386bbba44.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end. We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.
Conflicts:
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/u-boot.lds
arch/arm/lib/Makefile
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/dvlhost/u-boot.lds
board/freescale/mx31ads/u-boot.lds
doc/README.scrapyard
include/configs/tegra-common.h
Build tested for all of ARM and run-time tested on am335x_evm.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board')
227 files changed, 4349 insertions, 1978 deletions
diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds index 7c1695a..c72043d 100644 --- a/board/BuS/eb_cpu5282/u-boot.lds +++ b/board/BuS/eb_cpu5282/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index ee2c705..2b76e92 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -89,7 +89,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index a507d73..3334a44 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index dc8c4e9..e88bd97 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index a507d73..3334a44 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index dc8c4e9..e88bd97 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index a507d73..3334a44 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index b43a1e4..88c410c 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index 646931a..84bb763 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index a0d217b..c76728a 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -41,15 +41,15 @@ SECTIONS *(.text*) } - . = ALIGN (4); + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - . = ALIGN (4); + . = ALIGN(4); .data : { *(.data*) } - . = ALIGN (4); + . = ALIGN(4); .got : { *(.got) } @@ -57,7 +57,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN (4); @@ -72,13 +72,21 @@ SECTIONS *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + _end = .; + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - _end = .; + __bss_end = .; } - __bss_end =.; + .bss_end __bss_end (OVERLAY) : { + KEEP(*(__bss_end)); + } + /DISCARD/ : { *(.dynstr*) } /DISCARD/ : { *(.dynamic*) } /DISCARD/ : { *(.plt*) } diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index da2b4e2..984f70e 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -41,15 +41,15 @@ SECTIONS *(.text*) } - . = ALIGN (4); + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - . = ALIGN (4); + . = ALIGN(4); .data : { *(.data*) } - . = ALIGN (4); + . = ALIGN(4); .got : { *(.got) } @@ -57,7 +57,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN (4); @@ -72,13 +72,21 @@ SECTIONS *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + _end = .; + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - _end = .; + __bss_end = .; } - __bss_end =.; + .bss_end __bss_end (OVERLAY) : { + KEEP(*(__bss_end)); + } + /DISCARD/ : { *(.dynstr*) } /DISCARD/ : { *(.dynamic*) } /DISCARD/ : { *(.plt*) } diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index f922033..fc48cf0 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN (4); @@ -72,13 +72,21 @@ SECTIONS *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + _end = .; + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - _end = .; + __bss_end = .; } - __bss_end =.; + .bss_end __bss_end (OVERLAY) : { + KEEP(*(__bss_end)); + } + /DISCARD/ : { *(.dynstr*) } /DISCARD/ : { *(.dynamic*) } /DISCARD/ : { *(.plt*) } diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index 2f10e7c..def2f1f 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index d6b66d4..dd9d52d 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -48,10 +48,6 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { - #include <u-boot.lst> - } >.sram - . = ALIGN(4); .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds index bf7600a..f309598 100644 --- a/board/altera/nios2-generic/u-boot.lds +++ b/board/altera/nios2-generic/u-boot.lds @@ -49,7 +49,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } /* INIT DATA sections - "Small" data (see the gcc -G option) diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index 3bdad34..e9f026f 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -74,7 +74,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index 1f9a4ae..209f484 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -75,7 +75,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index 0396c9f..3d61613 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -75,7 +75,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index 3bdad34..e9f026f 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -74,7 +74,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index 9a2a232..2ea3944 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -75,7 +75,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds index e853da8..1b537f6 100644 --- a/board/amcc/sequoia/u-boot-ram.lds +++ b/board/amcc/sequoia/u-boot-ram.lds @@ -66,7 +66,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds index 11aa092..264e43f 100644 --- a/board/astro/mcf5373l/u-boot.lds +++ b/board/astro/mcf5373l/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 2555672..3aa394a 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -157,13 +157,18 @@ int board_early_init_f(void) int board_init(void) { +#ifdef CONFIG_AT91SAM9G20EK_2MMC + /* arch number of AT91SAM9G20EK_2MMC-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK_2MMC; +#else #ifdef CONFIG_AT91SAM9G20EK - /* arch number of AT91SAM9260EK-Board */ + /* arch number of AT91SAM9G20EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK; #else /* arch number of AT91SAM9260EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; #endif +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index e6a932e..ea95e43 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -33,13 +33,8 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/mmc.h> #include <asm/arch-tegra/sys_proto.h> #include <asm/arch-tegra/uart.h> -#ifdef CONFIG_TEGRA_MMC -#include <mmc.h> -#endif - #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) @@ -54,7 +49,7 @@ void gpio_early_init(void) * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); /* for write-protect GPIO PI6 */ @@ -62,16 +57,4 @@ static void pin_mux_mmc(void) /* for CD GPIO PH2 */ pinmux_tristate_disable(PINGRP_ATD); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - /* init dev 0, SD slot, with 4-bit bus */ - tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); - - return 0; -} #endif diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts index e46afbe..a9a07f9 100644 --- a/board/avionic-design/dts/tegra20-medcom-wide.dts +++ b/board/avionic-design/dts/tegra20-medcom-wide.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Medcom-Wide"; @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts index 3e6cce0..20016f2 100644 --- a/board/avionic-design/dts/tegra20-plutux.dts +++ b/board/avionic-design/dts/tegra20-plutux.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Plutux"; @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/board/avionic-design/dts/tegra20-tamonten.dtsi new file mode 100644 index 0000000..86c7bab --- /dev/null +++ b/board/avionic-design/dts/tegra20-tamonten.dtsi @@ -0,0 +1,489 @@ +#include "tegra20.dtsi" + +/ { + model = "Avionic Design Tamonten SOM"; + compatible = "ad,tamonten", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + host1x { + hdmi { + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <0>; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = <1>; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <2>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = <0>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + status = "okay"; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + status = "okay"; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + status = "okay"; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + sm0 { + regulator-name = "vdd_sys_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sys_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sys_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + ldo0 { + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + }; + }; + + pmc { + nvidia,invert-interrupt; + }; + + usb@c5008000 { + status = "okay"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 1>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + bus-width = <4>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index bf3ff1d..1d7cf89 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Tamonten Evaluation Carrier"; @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg new file mode 100644 index 0000000..16a37d0 --- /dev/null +++ b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000..0607703 --- /dev/null +++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/6x_bootscript.txt b/board/boundary/nitrogen6x/6x_bootscript.txt new file mode 100644 index 0000000..061b3a4 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript.txt @@ -0,0 +1,63 @@ +setenv bootargs enable_wait_mode=off +setenv nextcon 0; + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + setenv fbmem "fbmem=28M"; + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +i2c dev 2 +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs $fbmem +setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait" + +if test "sata" = "${dtype}" ; then + setenv bootargs "$bootargs root=/dev/sda1" ; +else + setenv "bootargs $bootargs root=/dev/mmcblk0p1" ; +fi +${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ; +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_bootscript_android.txt b/board/boundary/nitrogen6x/6x_bootscript_android.txt new file mode 100644 index 0000000..0982cf8 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript_android.txt @@ -0,0 +1,64 @@ +${dtype} dev ${disk} + +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; + +i2c dev 2 + +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=28M"; + else + setenv fbcon ${fbcon},28M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs fbcon=$fbcon +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt new file mode 100644 index 0000000..0982cf8 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt @@ -0,0 +1,64 @@ +${dtype} dev ${disk} + +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; + +i2c dev 2 + +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=28M"; + else + setenv fbcon ${fbcon},28M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs fbcon=$fbcon +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt new file mode 100644 index 0000000..0d8e8e5 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_upgrade.txt @@ -0,0 +1,45 @@ +setenv stdout serial,vga +echo "check U-Boot" ; +setenv offset 0x400 +if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then + echo "read $filesize bytes from SD card" ; + if sf probe || sf probe || \ + sf probe 1 27000000 || sf probe 1 27000000 ; then + echo "probed SPI ROM" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + echo "------- U-Boot versions match" ; + else + echo "Need U-Boot upgrade" ; + echo "Program in 5 seconds" ; + for n in 5 4 3 2 1 ; do + echo $n ; + sleep 1 ; + done + echo "erasing" ; + sf erase 0 0x50000 ; + # two steps to prevent bricking + echo "programming" ; + sf write 0x12000000 $offset $filesize ; + echo "verifying" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + while echo "---- U-Boot upgraded. reset" ; do + sleep 120 + done + else + echo "Read verification error" ; + fi + else + echo "Error re-reading EEPROM" ; + fi + fi + else + echo "Error reading boot loader from EEPROM" ; + fi + else + echo "Error initializing EEPROM" ; + fi ; +else + echo "No U-Boot image found on SD card" ; +fi diff --git a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg new file mode 100644 index 0000000..de33e65 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg new file mode 100644 index 0000000..19707cf --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg new file mode 100644 index 0000000..dd6a423 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg new file mode 100644 index 0000000..d5d06e2 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile new file mode 100644 index 0000000..fe1e5e0 --- /dev/null +++ b/board/boundary/nitrogen6x/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de> +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := nitrogen6x.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README new file mode 100644 index 0000000..5049093 --- /dev/null +++ b/board/boundary/nitrogen6x/README @@ -0,0 +1,92 @@ +U-Boot for the Boundary Devices Nitrogen6X and +Freescale i.MX6Q SabreLite boards + +This file contains information for the port of +U-Boot to the Boundary Devices Nitrogen6X and +Freescale i.MX6Q SabreLite boards. + +1. Boot source, boot from SPI NOR +--------------------------------- +The configuration in this directory supports both the +Nitrogen6X and Freescale SabreLite board, but in a +different fashion from Freescale's implementation in +board/freescale/mx6qsabrelite. + +In particular, this image supports booting from SPI NOR +and saving the environment to SPI NOR. + +It does not support 'boot from SD' at offset 0x400 +except through the 'bmode' command. + http://lists.denx.de/pipermail/u-boot/2012-August/131151.html + +2. Boots using 6x_bootscript on SATA or SD card +----------------------------------------------- +The default bootcmd for these boards is configured +to look for and source a boot script named '6x_bootscript' +in the root of the first partition of the following +devices: + + sata 0 + mmc 0 + mmc 1 + +They're searched in the order listed above, trying both the +ext2 and fat filesystems. + +2. Maintaining the SPI NOR +-------------------------- +A couple of convenience commands + + clearenv - clear environment to factory default + upgradeu - look and source a boot script named + '6x_upgrade' to upgrade the U-Boot version + in SPI NOR. The search is the same as for + 6x_bootscript described above. + +3. Display support +------------------ +U-Boot support for the following displays is configured by +default: + + HDMI - 1024 x 768 for maximum compatibility + Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1) + wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600) + wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480) + +Since the ipuv3_fb display driver currently supports only a single display, +this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect +or the I2C touch controller of the LVDS and RGB displays in the priority +listed above. + +Setting 'panel' environment variable to one of the names above will +override auto-detection and force activation of the specified panel. + +4. Building +------------ + +To build U-Boot for one of the Nitrogen6x or SabreLite board: + + make nitrogen6x_config + make u-boot.imx + +Note that 'nitrogen6x' is a placeholder. The complete list of supported +board configurations is shown in tha MAINTAINERS file: + nitrogen6q i.MX6Q/6D 1GB + nitrogen6dl i.MX6DL 1GB + nitrogen6s i.MX6S 512MB + nitrogen6q2g i.MX6Q/6D 2GB + nitrogen6dl2g i.MX6DL 2GB + nitrogen6s1g i.MX6S 1GB + +The -6q variants support either the i.MX6Quad or i.MX6Dual processors +and are configured for a 64-bit memory bus at 1066 MHz. + +The -6dl variants also use a 64-bit memory bus, operated at 800MHz. + +The -6s variants use a 32-bit memory bus at 800MHz. + +If you place the u-boot.imx into a single-partition SD card +along with a binary version of the boot script 6x_upgrade.txt, +you can program it using 'upgradeu': + + U-Boot> run upgradeu diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg new file mode 100644 index 0000000..e7d1f86 --- /dev/null +++ b/board/boundary/nitrogen6x/clocks.cfg @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg new file mode 100644 index 0000000..c315812 --- /dev/null +++ b/board/boundary/nitrogen6x/ddr-setup.cfg @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +/* + * MDSCR con_req + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg new file mode 100644 index 0000000..d6da96c --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_4x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg new file mode 100644 index 0000000..0b1c35c --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg new file mode 100644 index 0000000..680a853 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg new file mode 100644 index 0000000..f57ab0e --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg new file mode 100644 index 0000000..b5af5cc --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_2x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg new file mode 100644 index 0000000..5aeefc8 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_2x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c new file mode 100644 index 0000000..229c237 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -0,0 +1,895 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <malloc.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/boot_mode.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mxc_hdmi.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +int dram_init(void) +{ + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1, SGTL5000 */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2 Camera, MIPI */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3, J15 - RGB connector */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +/* wl1271 pads on nitrogen6x */ +iomux_v3_cfg_t const wl12xx_pads[] = { + (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(WEAK_PULLDOWN), + (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(OUTPUT_40OHM), + (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(OUTPUT_40OHM), +}; +#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) +#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) +#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) + +/* Button assignments for J14 */ +static iomux_v3_cfg_t const button_pads[] = { + /* Menu */ + MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Back */ + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Labelled Search (mapped to Power under Android) */ + MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Home */ + MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Down */ + MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Up */ + MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ + gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ + gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +iomux_v3_cfg_t const usb_pads[] = { + MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB hub */ + gpio_direction_output(IMX_GPIO_NR(7, 12), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(7, 12), 1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(7, 0)); + ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); + } else { + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} +#endif + +u32 get_board_rev(void) +{ + return 0x63000; +} + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +void setup_spi(void) +{ + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +static void setup_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, + ARRAY_SIZE(button_pads)); +} + +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB + |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V + |IOMUXC_GPR13_SATA_PHY_1_SLOW); + + return 0; +} +#endif + +#if defined(CONFIG_VIDEO_IPUV3) + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight on RGB connector: J15 */ + MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) + + /* Backlight on LVDS connector: J6 */ + MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) +}; + +static iomux_v3_cfg_t const rgb_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, + MX6_PAD_DI0_PIN4__GPIO_4_20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, +}; + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + + +static int detect_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; +} + +static void enable_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + printf("%s: setup HDMI monitor\n", __func__); + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return ((0 == i2c_set_bus_num(dev->bus)) + && + (0 == i2c_probe(dev->addr))); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + rgb_pads, + ARRAY_SIZE(rgb_pads)); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); +} + +static struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x38, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "wsvga-lvds", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x48, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_rgb, + .mode = { + .name = "wvga-rgb", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 37037, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + } + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + ret = -EINVAL; + } + return (0 != ret); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + + int reg; + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET + |MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* Turn on HDMI PHY clock */ + reg = __raw_readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK + |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + + /* clear HDMI PHY reset */ + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + + /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ + writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); + writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + |(CHSCCDR_PODF_DIVIDE_BY_3 + <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + |(CHSCCDR_IPU_PRE_CLK_540M_PFD + <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + gpio_direction_input(LVDS_BACKLIGHT_GP); + gpio_direction_input(RGB_BACKLIGHT_GP); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + /* Disable wl1271 For Nitrogen6w */ + gpio_direction_input(WL12XX_WL_IRQ_GP); + gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); + gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); + + imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); + setup_buttons(); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int checkboard(void) +{ + if (gpio_get_value(WL12XX_WL_IRQ_GP)) + puts("Board: Nitrogen6X\n"); + else + puts("Board: SABRE Lite\n"); + + return 0; +} + +struct button_key { + char const *name; + unsigned gpnum; + char ident; +}; + +static struct button_key const buttons[] = { + {"back", IMX_GPIO_NR(2, 2), 'B'}, + {"home", IMX_GPIO_NR(2, 4), 'H'}, + {"menu", IMX_GPIO_NR(2, 1), 'M'}, + {"search", IMX_GPIO_NR(2, 3), 'S'}, + {"volup", IMX_GPIO_NR(7, 13), 'V'}, + {"voldown", IMX_GPIO_NR(4, 5), 'v'}, +}; + +/* + * generate a null-terminated string containing the buttons pressed + * returns number of keys pressed + */ +static int read_keys(char *buf) +{ + int i, numpressed = 0; + for (i = 0; i < ARRAY_SIZE(buttons); i++) { + if (!gpio_get_value(buttons[i].gpnum)) + buf[numpressed++] = buttons[i].ident; + } + buf[numpressed] = '\0'; + return numpressed; +} + +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char envvalue[ARRAY_SIZE(buttons)+1]; + int numpressed = read_keys(envvalue); + setenv("keybd", envvalue); + return numpressed == 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "Tests for keypresses, sets 'keybd' environment variable", + "Returns 0 (true) to shell if key is pressed." +); + +#ifdef CONFIG_PREBOOT +static char const kbd_magic_prefix[] = "key_magic"; +static char const kbd_command_prefix[] = "key_cmd"; + +static void preboot_keys(void) +{ + int numpressed; + char keypress[ARRAY_SIZE(buttons)+1]; + numpressed = read_keys(keypress); + if (numpressed) { + char *kbd_magic_keys = getenv("magic_keys"); + char *suffix; + /* + * loop over all magic keys + */ + for (suffix = kbd_magic_keys; *suffix; ++suffix) { + char *keys; + char magic[sizeof(kbd_magic_prefix) + 1]; + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + keys = getenv(magic); + if (keys) { + if (!strcmp(keys, keypress)) + break; + } + } + if (*suffix) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + if (cmd) { + setenv("preboot", cmd); + return; + } + } + } +} +#endif + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_PREBOOT + preboot_keys(); +#endif + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} diff --git a/board/cm_t35/Makefile b/board/cm_t35/Makefile index 894fa09..bde56e6 100644 --- a/board/cm_t35/Makefile +++ b/board/cm_t35/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o +COBJS-$(CONFIG_LCD) += display.o COBJS := cm_t35.o leds.o $(COBJS-y) diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index edbb941..e0e8235 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -33,6 +33,7 @@ #include <net.h> #include <i2c.h> #include <usb.h> +#include <mmc.h> #include <twl4030.h> #include <linux/compiler.h> @@ -216,6 +217,9 @@ static void cm_t3x_set_common_muxconf(void) /* SB-T35 Ethernet */ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ + /* DVI enable */ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ + /* CM-T3x Ethernet */ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ @@ -377,9 +381,19 @@ void set_muxconf_regs(void) } #ifdef CONFIG_GENERIC_MMC +int board_mmc_getcd(struct mmc *mmc) +{ + u8 val; + + if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, TWL4030_BASEADD_GPIO)) + return -1; + + return !(val & 1); +} + int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1, 59); } #endif diff --git a/board/cm_t35/display.c b/board/cm_t35/display.c new file mode 100644 index 0000000..2f78bad --- /dev/null +++ b/board/cm_t35/display.c @@ -0,0 +1,428 @@ +/* + * (C) Copyright 2012 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Nikita Kiryanov <nikita@compulab.co.il> + * + * Parsing code based on linux/drivers/video/pxafb.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <stdio_dev.h> +#include <asm/arch/dss.h> +#include <lcd.h> +#include <asm/arch-omap3/dss.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum display_type { + NONE, + DVI, + DVI_CUSTOM, +}; + +#define CMAP_ADDR 0x80100000 + +/* + * The frame buffer is allocated before we have the chance to parse user input. + * To make sure enough memory is allocated for all resolutions, we define + * vl_{col | row} to the maximal resolution supported by OMAP3. + */ +vidinfo_t panel_info = { + .vl_col = 1400, + .vl_row = 1050, + .vl_bpix = LCD_BPP, + .cmap = (ushort *)CMAP_ADDR, +}; + +static struct panel_config panel_cfg; +static enum display_type lcd_def; + +/* + * A note on DVI presets; + * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can + * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to + * support two BMP types with one setting. + */ +static const struct panel_config preset_dvi_640X480 = { + .lcd_size = PANEL_LCD_SIZE(640, 480), + .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), + .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), + .divisor = 12 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_800X600 = { + .lcd_size = PANEL_LCD_SIZE(800, 600), + .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), + .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), + .divisor = 8 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1024X768 = { + .lcd_size = PANEL_LCD_SIZE(1024, 768), + .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), + .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), + .divisor = 5 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1152X864 = { + .lcd_size = PANEL_LCD_SIZE(1152, 864), + .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), + .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X960 = { + .lcd_size = PANEL_LCD_SIZE(1280, 960), + .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), + .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X1024 = { + .lcd_size = PANEL_LCD_SIZE(1280, 1024), + .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), + .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +/* + * set_resolution_params() + * + * Due to usage of multiple display related APIs resolution data is located in + * more than one place. This function updates them all. + */ +static void set_resolution_params(int x, int y) +{ + panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y); + panel_info.vl_col = x; + panel_info.vl_row = y; + lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; +} + +static void set_preset(const struct panel_config preset, int x_res, int y_res) +{ + panel_cfg = preset; + set_resolution_params(x_res, y_res); +} + +static enum display_type set_dvi_preset(const struct panel_config preset, + int x_res, int y_res) +{ + set_preset(preset, x_res, y_res); + return DVI; +} + +/* + * parse_mode() - parse the mode parameter of custom lcd settings + * + * @mode: <res_x>x<res_y> + * + * Returns -1 on error, 0 on success. + */ +static int parse_mode(const char *mode) +{ + unsigned int modelen = strlen(mode); + int res_specified = 0; + unsigned int xres = 0, yres = 0; + int yres_specified = 0; + int i; + + for (i = modelen - 1; i >= 0; i--) { + switch (mode[i]) { + case 'x': + if (!yres_specified) { + yres = simple_strtoul(&mode[i + 1], NULL, 0); + yres_specified = 1; + } else { + goto done_parsing; + } + + break; + case '0' ... '9': + break; + default: + goto done_parsing; + } + } + + if (i < 0 && yres_specified) { + xres = simple_strtoul(mode, NULL, 0); + res_specified = 1; + } + +done_parsing: + if (res_specified) { + set_resolution_params(xres, yres); + } else { + printf("LCD: invalid mode: %s\n", mode); + return -1; + } + + return 0; +} + +#define PIXEL_CLK_NUMERATOR (26 * 432 / 39) +/* + * parse_pixclock() - Parse the pixclock parameter of custom lcd settings + * + * @pixclock: the desired pixel clock + * + * Returns -1 on error, 0 on success. + * + * Handling the pixel_clock: + * + * Pixel clock is defined in the OMAP35x TRM as follows: + * pixel_clock = + * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) / + * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] * + * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1)) + * + * In practice, this means that in order to set the + * divisor for the desired pixel clock one needs to + * solve the following equation: + * + * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0] + * + * NOTE: the explicit equation above is reduced. Do not + * try to infer anything from these numbers. + */ +static int parse_pixclock(char *pixclock) +{ + int divisor, pixclock_val; + char *pixclk_start = pixclock; + + pixclock_val = simple_strtoul(pixclock, &pixclock, 10); + divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val); + /* 0 and 1 are illegal values for PCD */ + if (divisor <= 1) + divisor = 2; + + panel_cfg.divisor = divisor | (1 << 16); + if (pixclock[0] != '\0') { + printf("LCD: invalid value for pixclock:%s\n", pixclk_start); + return -1; + } + + return 0; +} + +/* + * parse_setting() - parse a single setting of custom lcd parameters + * + * @setting: The custom lcd setting <name>:<value> + * + * Returns -1 on failure, 0 on success. + */ +static int parse_setting(char *setting) +{ + int num_val; + char *setting_start = setting; + + if (!strncmp(setting, "mode:", 5)) { + return parse_mode(setting + 5); + } else if (!strncmp(setting, "pixclock:", 9)) { + return parse_pixclock(setting + 9); + } else if (!strncmp(setting, "left:", 5)) { + num_val = simple_strtoul(setting + 5, &setting, 0); + panel_cfg.timing_h |= DSS_HBP(num_val); + } else if (!strncmp(setting, "right:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_h |= DSS_HFP(num_val); + } else if (!strncmp(setting, "upper:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VBP(num_val); + } else if (!strncmp(setting, "lower:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VFP(num_val); + } else if (!strncmp(setting, "hsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_h |= DSS_HSW(num_val); + } else if (!strncmp(setting, "vsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_v |= DSS_VSW(num_val); + } else if (!strncmp(setting, "hsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IHS; + else + panel_cfg.pol_freq &= ~DSS_IHS; + } else if (!strncmp(setting, "vsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IVS; + else + panel_cfg.pol_freq &= ~DSS_IVS; + } else if (!strncmp(setting, "outputen:", 9)) { + if (simple_strtoul(setting + 9, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IEO; + else + panel_cfg.pol_freq &= ~DSS_IEO; + } else if (!strncmp(setting, "pixclockpol:", 12)) { + if (simple_strtoul(setting + 12, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IPC; + else + panel_cfg.pol_freq &= ~DSS_IPC; + } else if (!strncmp(setting, "active", 6)) { + panel_cfg.panel_type = ACTIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "passive", 7)) { + panel_cfg.panel_type = PASSIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "display:", 8)) { + if (!strncmp(setting + 8, "dvi", 3)) { + lcd_def = DVI_CUSTOM; + return 0; /* Avoid sanity check below */ + } + } else { + printf("LCD: unknown option %s\n", setting_start); + return -1; + } + + if (setting[0] != '\0') { + printf("LCD: invalid value for %s\n", setting_start); + return -1; + } + + return 0; +} + +/* + * env_parse_customlcd() - parse custom lcd params from an environment variable. + * + * @custom_lcd_params: The environment variable containing the lcd params. + * + * Returns -1 on failure, 0 on success. + */ +static int parse_customlcd(char *custom_lcd_params) +{ + char params_cpy[160]; + char *setting; + + strncpy(params_cpy, custom_lcd_params, 160); + setting = strtok(params_cpy, ","); + while (setting) { + if (parse_setting(setting) < 0) + return -1; + + setting = strtok(NULL, ","); + } + + /* Currently we don't support changing this via custom lcd params */ + panel_cfg.data_lines = LCD_INTERFACE_24_BIT; + panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */ + + return 0; +} + +/* + * env_parse_displaytype() - parse display type. + * + * Parses the environment variable "displaytype", which contains the + * name of the display type or preset, in which case it applies its + * configurations. + * + * Returns the type of display that was specified. + */ +static enum display_type env_parse_displaytype(char *displaytype) +{ + if (!strncmp(displaytype, "dvi640x480", 10)) + return set_dvi_preset(preset_dvi_640X480, 640, 480); + else if (!strncmp(displaytype, "dvi800x600", 10)) + return set_dvi_preset(preset_dvi_800X600, 800, 600); + else if (!strncmp(displaytype, "dvi1024x768", 11)) + return set_dvi_preset(preset_dvi_1024X768, 1024, 768); + else if (!strncmp(displaytype, "dvi1152x864", 11)) + return set_dvi_preset(preset_dvi_1152X864, 1152, 864); + else if (!strncmp(displaytype, "dvi1280x960", 11)) + return set_dvi_preset(preset_dvi_1280X960, 1280, 960); + else if (!strncmp(displaytype, "dvi1280x1024", 12)) + return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024); + + return NONE; +} + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; +void *lcd_base; +short console_col; +short console_row; +void *lcd_console_address; + +void lcd_ctrl_init(void *lcdbase) +{ + struct prcm *prcm = (struct prcm *)PRCM_BASE; + char *custom_lcd; + char *displaytype = getenv("displaytype"); + + if (displaytype == NULL) + return; + + lcd_def = env_parse_displaytype(displaytype); + /* If we did not recognize the preset, check if it's an env variable */ + if (lcd_def == NONE) { + custom_lcd = getenv(displaytype); + if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0) + return; + } + + panel_cfg.frame_buffer = lcdbase; + omap3_dss_panel_config(&panel_cfg); + /* + * Pixel clock is defined with many divisions and only few + * multiplications of the system clock. Since DSS FCLK divisor is set + * to 16 by default, we need to set it to a smaller value, like 3 + * (chosen via trial and error). + */ + clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); +} + +void lcd_enable(void) +{ + if (lcd_def == DVI || lcd_def == DVI_CUSTOM) { + gpio_direction_output(54, 0); /* Turn on DVI */ + omap3_dss_enable(); + } +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {} diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index 47378fd..809a705 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 1cc482f..1f006d7 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index dc8c4e9..e88bd97 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index c6c1071..2dca275 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -147,8 +147,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts index 31b064d..780203c 100644 --- a/board/compal/dts/tegra20-paz00.dts +++ b/board/compal/dts/tegra20-paz00.dts @@ -1,13 +1,15 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { - model = "Toshiba AC100 / Dynabook AZ"; - compatible = "compal,paz00", "nvidia,tegra20"; + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000000"; }; memory { @@ -53,6 +55,19 @@ status = "disabled"; }; + sdhci@c8000000 { + status = "okay"; + cd-gpios = <&gpio 173 1>; /* gpio PV5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 169 0>; /* gpio PV1 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; + lcd_panel: panel { /* PAZ00 has 1024x600 */ clock = <54030000>; diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 1447f47..d6e5c37 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -18,19 +18,14 @@ #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_TEGRA_MMC -#include <mmc.h> -#endif - #ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { /* SDMMC4: config 3, x8 on 2nd set of pins */ pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); @@ -51,25 +46,6 @@ static void pin_mux_mmc(void) /* For CD GPIO PV5 */ pinmux_tristate_disable(PINGRP_GPV); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - debug("board_mmc_init: init eMMC\n"); - /* init dev 0, eMMC chip, with 8-bit bus */ - tegra_mmc_init(0, 8, -1, -1); - - debug("board_mmc_init: init SD slot\n"); - /* init dev 3, SD slot, with 4-bit bus */ - tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); - - return 0; -} #endif #ifdef CONFIG_LCD diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts index 7aeed67..ee31476 100644 --- a/board/compulab/dts/tegra20-trimslice.dts +++ b/board/compulab/dts/tegra20-trimslice.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "Compulab TrimSlice board"; @@ -9,6 +9,8 @@ aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000000"; }; memory { @@ -47,4 +49,16 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000000 { + status = "okay"; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 121 1>; /* gpio PP1 */ + wp-gpios = <&gpio 122 0>; /* gpio PP2 */ + bus-width = <4>; + }; }; diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 8f4dd09..8401100 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -27,12 +27,8 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> #include <i2c.h> -#ifdef CONFIG_TEGRA_MMC -#include <mmc.h> -#endif void pin_mux_usb(void) { @@ -52,7 +48,7 @@ void pin_mux_spi(void) * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); @@ -60,20 +56,3 @@ static void pin_mux_mmc(void) /* For CD GPIO PP1 */ pinmux_tristate_disable(PINGRP_DAP3); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */ - tegra_mmc_init(0, 4, -1, GPIO_PP1); - - /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */ - tegra_mmc_init(3, 4, -1, -1); - - return 0; -} diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 56fe495..5c02eaf 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -80,7 +80,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD)) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index d7a2e56..99cbed4 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 512fe1a..663100e 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -77,7 +77,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 6d287f1..bc34fb5 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -49,11 +49,6 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { - #include <u-boot.lst> - } >.sram - - . = ALIGN(4); .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index e3a07cc..2557830 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -58,11 +58,6 @@ SECTIONS } . = ALIGN(4); - .u_boot_list : { - #include <u-boot.lst> - } - - . = ALIGN(4); __rel_dyn_start = .; __rel_dyn_end = .; __dynsym_start = .; diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index d93efaf..aff7c1f 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -57,6 +57,10 @@ int board_early_init_f(void) mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0); + + mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 | + MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); + gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0); #endif return 0; diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index ed91003..b13d3e1 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN (4); @@ -72,13 +72,21 @@ SECTIONS *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + _end = .; + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - _end = .; + __bss_end = .; } - __bss_end =.; + .bss_end __bss_end (OVERLAY) : { + KEEP(*(__bss_end)); + } + /DISCARD/ : { *(.dynstr*) } /DISCARD/ : { *(.dynamic*) } /DISCARD/ : { *(.plt*) } diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index 3c1c05a..a1481c8 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index 92796e6..614bbb2 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index 155fa76..e3f7d80 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -70,7 +70,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index 7baaad8..c00b3c3 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index cb94a51..4297b8b 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -76,7 +76,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index 101b893..6a5cef6 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -104,7 +104,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index fd77fa9..a4d9da7 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 7ffdc17..642f1c9 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -77,7 +77,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index 4b956f8..44c61eb 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index 1cb191c..0e2206c 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index 3c1c05a..a1481c8 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index 92796e6..614bbb2 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd40..f4cae5e 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -109,12 +109,12 @@ DATA 4 0x021b4828 0x33333333 DATA 4 0x021b0018 0x00081740 DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005B0E21 +DATA 4 0x021b0030 0x005A1023 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 @@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033 DATA 4 0x021b001c 0x0000803B DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038 DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008048 diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds index da4b4f2..6f80e41 100644 --- a/board/freescale/m5208evbe/u-boot.lds +++ b/board/freescale/m5208evbe/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index e3f8847..9db171e 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds index c324b64..f11d483 100644 --- a/board/freescale/m5235evb/u-boot.lds +++ b/board/freescale/m5235evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds index 47378fd..809a705 100644 --- a/board/freescale/m5249evb/u-boot.lds +++ b/board/freescale/m5249evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds index d14a2af..9de8885 100644 --- a/board/freescale/m5253demo/u-boot.lds +++ b/board/freescale/m5253demo/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds index 47378fd..809a705 100644 --- a/board/freescale/m5253evbe/u-boot.lds +++ b/board/freescale/m5253evbe/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds index c7574c9..82b67d5 100644 --- a/board/freescale/m5271evb/u-boot.lds +++ b/board/freescale/m5271evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds index 47378fd..809a705 100644 --- a/board/freescale/m5272c3/u-boot.lds +++ b/board/freescale/m5272c3/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds index 7f3b73d..fda4cf4 100644 --- a/board/freescale/m5275evb/u-boot.lds +++ b/board/freescale/m5275evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index 35d669c..cdfd0e4 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index 1a6f0cd..c40c565 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds index f5cc586..f803e4a 100644 --- a/board/freescale/m5329evb/u-boot.lds +++ b/board/freescale/m5329evb/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds index 11aa092..264e43f 100644 --- a/board/freescale/m5373evb/u-boot.lds +++ b/board/freescale/m5373evb/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m54418twr/u-boot.lds b/board/freescale/m54418twr/u-boot.lds index 5ae7fce..3247dbf 100644 --- a/board/freescale/m54418twr/u-boot.lds +++ b/board/freescale/m54418twr/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m54451evb/u-boot.lds b/board/freescale/m54451evb/u-boot.lds index 2bd4a73..fd1289e 100644 --- a/board/freescale/m54451evb/u-boot.lds +++ b/board/freescale/m54451evb/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds index 5ae7fce..3247dbf 100644 --- a/board/freescale/m54455evb/u-boot.lds +++ b/board/freescale/m54455evb/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds index 5e987bb..bbe36f0 100644 --- a/board/freescale/m547xevb/u-boot.lds +++ b/board/freescale/m547xevb/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds index 27340ee..9315927 100644 --- a/board/freescale/m548xevb/u-boot.lds +++ b/board/freescale/m548xevb/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index 6007433..b6f4e7e 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; +#define HW_DRAM_CTL14 (0x38 >> 2) +#define CS_MAP 0x3 +#define INTAREF 0x2 +#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP) + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG; +} + void board_init_ll(void) { mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 4d1858b..264c4e8 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); @@ -80,11 +80,17 @@ SECTIONS _end = .; - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { + *(.bss*) . = ALIGN(4); - __bss_end = .; + __bss_end = .; + } + .bss_end __bss_end (OVERLAY) : { + KEEP(*(__bss_end)); } /DISCARD/ : { *(.bss*) } diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index ee20d4f..ff7f5e8 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -23,7 +23,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx6x_pins.h> +#include <asm/arch/mx6q_pins.h> #include <asm/arch/clock.h> #include <asm/errno.h> #include <asm/gpio.h> @@ -55,53 +55,53 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 9e3700e..91cc007 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -22,7 +22,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> -#include <asm/arch/mx6x_pins.h> +#include <asm/arch/mx6q_pins.h> #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> @@ -54,26 +54,26 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -82,18 +82,18 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index f010d0c..5b69a6d 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -25,7 +25,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> -#include <asm/arch/mx6x_pins.h> +#include <asm/arch/mx6q_pins.h> #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> @@ -46,12 +46,12 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ @@ -72,19 +72,19 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - return 0; + return 0; } iomux_v3_cfg_t const uart1_pads[] = { - MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart2_pads[] = { - MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -92,13 +92,13 @@ iomux_v3_cfg_t const uart2_pads[] = { /* I2C1, SGTL5000 */ struct i2c_pads_info i2c_pad_info0 = { .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC, + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, .gp = IMX_GPIO_NR(3, 21) }, .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC, + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, .gp = IMX_GPIO_NR(3, 28) } }; @@ -106,13 +106,13 @@ struct i2c_pads_info i2c_pad_info0 = { /* I2C2 Camera, MIPI */ struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC, + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, .gp = IMX_GPIO_NR(4, 12) }, .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -120,86 +120,86 @@ struct i2c_pads_info i2c_pad_info1 = { /* I2C3, J15 - RGB connector */ struct i2c_pads_info i2c_pad_info2 = { .scl = { - .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC, + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, .gp = IMX_GPIO_NR(1, 5) }, .sda = { - .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC, + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, .gp = IMX_GPIO_NR(7, 11) } }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { - MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 32 - 1 - (MODE0) all */ - MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 31 - 1 - (MODE1) all */ - MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 28 - 1 - (MODE2) all */ - MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 27 - 1 - (MODE3) all */ - MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 42 PHY nRST */ - MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads2[] = { - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; /* Button assignments for J14 */ static iomux_v3_cfg_t const button_pads[] = { /* Menu */ - MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Back */ - MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Labelled Search (mapped to Power under Android) */ - MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Home */ - MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Down */ - MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Up */ - MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -221,13 +221,13 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usb_pads[] = { - MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } #ifdef CONFIG_USB_EHCI_MX6 @@ -246,55 +246,55 @@ int board_ehci_hcd_init(int port) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { gpio_direction_input(IMX_GPIO_NR(7, 0)); ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); - } else { + } else { gpio_direction_input(IMX_GPIO_NR(2, 6)); ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); - } + } - return ret; + return ret; } int board_mmc_init(bd_t *bis) { - s32 status = 0; - u32 index = 0; + s32 status = 0; + u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); break; default: - printf("Warning: you configured more USDHC controllers" + printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } + return status; + } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } - return status; + return status; } #endif @@ -306,10 +306,10 @@ u32 get_board_rev(void) #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ - MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), }; void setup_spi(void) @@ -403,44 +403,44 @@ int setup_sata(void) static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) /* Backlight on LVDS connector: J6 */ - MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) }; static iomux_v3_cfg_t const rgb_pads[] = { - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, - MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, - MX6Q_PAD_DI0_PIN4__GPIO_4_20, - MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, + MX6_PAD_DI0_PIN4__GPIO_4_20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, }; struct display_info_t { @@ -455,32 +455,26 @@ struct display_info_t { static int detect_hdmi(struct display_info_t const *dev) { - return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; } static void enable_hdmi(struct display_info_t const *dev) { + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; u8 reg; printf("%s: setup HDMI monitor\n", __func__); - reg = __raw_readb( - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + reg = readb(&hdmi->phy_conf0); reg |= HDMI_PHY_CONF0_PDZ_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + writeb(reg, &hdmi->phy_conf0); + udelay(3000); reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + writeb(reg, &hdmi->phy_conf0); udelay(3000); reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); - __raw_writeb(HDMI_MC_PHYRSTZ_ASSERT, - HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ); + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); } static int detect_i2c(struct display_info_t const *dev) @@ -638,6 +632,7 @@ static void setup_display(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; int reg; @@ -654,8 +649,7 @@ static void setup_display(void) writel(reg, &mxc_ccm->CCGR2); /* clear HDMI PHY reset */ - __raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT, - HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ); + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); @@ -732,8 +726,8 @@ int overwrite_console(void) int board_init(void) { - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_MXC_SPI setup_spi(); @@ -746,14 +740,14 @@ int board_init(void) setup_sata(); #endif - return 0; + return 0; } int checkboard(void) { - puts("Board: MX6Q-Sabre Lite\n"); + puts("Board: MX6Q-Sabre Lite\n"); - return 0; + return 0; } struct button_key { diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 65c4a1a..2b3926a 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -22,7 +22,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> -#include <asm/arch/mx6x_pins.h> +#include <asm/arch/mx6q_pins.h> #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> @@ -52,28 +52,28 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -87,44 +87,44 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc2_pads[] = { - MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static void setup_iomux_uart(void) diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds index 70ebf4d..60039cc 100644 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds index 429b579..ec73f73 100644 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ b/board/gaisler/gr_ep2s60/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds index 7052129..18dfb81 100644 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ b/board/gaisler/gr_xc3s_1500/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds index c608284..8de272e 100644 --- a/board/gaisler/grsim/u-boot.lds +++ b/board/gaisler/grsim/u-boot.lds @@ -87,7 +87,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds index eafb4f0..e57f734 100644 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ b/board/gaisler/grsim_leon2/u-boot.lds @@ -87,7 +87,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index f5c757e..30138dd 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -73,7 +73,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index d2649a8..08fb4aa 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 15575e4..b351a68 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -83,7 +83,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index e1cf249..a3aeb60 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index d2a2f22..8e58963 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -75,7 +75,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index e84cc79..4383c49 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 9fe6408..923461a 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -114,7 +114,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif @@ -130,6 +130,7 @@ static struct panel_config lcd_cfg = { .load_mode = 0x02, /* Frame Mode */ .panel_color = 0, .lcd_size = PANEL_LCD_SIZE(800, 480), + .gfx_format = GFXFORMAT_RGB24_UNPACKED, }; int board_video_init(void) diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index c9f0f37..5d1c2ad 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index dc8c4e9..e88bd97 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index 9ff187c..6e4939b 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 3e075a8..9995288 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds index fd77fa9..5b8d3b3 100644 --- a/board/idmr/u-boot.lds +++ b/board/idmr/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index a507d73..3334a44 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index e47aff0..0b34177 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 49fcf34..2bac916 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -150,8 +150,7 @@ static inline void setup_net_chip(void) {} #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index ea1e9ac..5ef22ae 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -34,10 +34,13 @@ const omap3_sysinfo sysinfo = { DDR_STACKED, #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) - "OMAP3 IGEP v2 board", + "IGEPv2", #endif #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) - "OMAP3 IGEP COM Module", + "IGEP COM MODULE/ELECTRON", +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) + "IGEP COM PROTON", #endif #if defined(CONFIG_ENV_IS_IN_ONENAND) "ONENAND", diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index 838c07b..1b43dbe 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index 53a19b2..bae9fb2 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index 90d2135..52c929c 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -110,7 +110,7 @@ SECTIONS . = .; .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index a507d73..3334a44 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index b43a1e4..88c410c 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index a507d73..3334a44 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index b43a1e4..88c410c 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 0b3721e..65e1b78 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -135,8 +135,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 12bcfcb..6e83aa2 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -140,7 +140,7 @@ int board_init(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 90b6b0f..c79a261 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -92,8 +92,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c index 8e18019..ad6ae36 100644 --- a/board/logicpd/zoom2/zoom2.c +++ b/board/logicpd/zoom2/zoom2.c @@ -183,8 +183,7 @@ void set_muxconf_regs (void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index 279605b..ce11a91 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 0a3e646..1d1b76a 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds index ac6af1a..d1bb127 100644 --- a/board/manroland/uc100/u-boot.lds +++ b/board/manroland/uc100/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c index dacc138..3fcf968 100644 --- a/board/matrix_vision/mvblx/fpga.c +++ b/board/matrix_vision/mvblx/fpga.c @@ -31,6 +31,7 @@ #include <ACEX1K.h> #include <command.h> #include <asm/gpio.h> +#include <linux/byteorder/generic.h> #include "fpga.h" #ifdef FPGA_DEBUG @@ -209,9 +210,20 @@ int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) { unsigned char *data = (unsigned char *) buf; int i; + int headerlen = len - cyclone2.size; + + if (headerlen < 0) + return FPGA_FAIL; + else if (headerlen == sizeof(uint32_t)) { + const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */ + char fpgavers_str[fpgavers_len]; + snprintf(fpgavers_str, fpgavers_len, "0x%08x", + be32_to_cpup((uint32_t*)data)); + setenv("fpgavers", fpgavers_str); + } fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) + for (i = headerlen; i < len; i++) _write_fpga(data[i]); fpga_debug("-%s\n", __func__); diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c index f68f312..49af384 100644 --- a/board/matrix_vision/mvblx/mvblx.c +++ b/board/matrix_vision/mvblx/mvblx.c @@ -106,8 +106,8 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - omap_mmc_init(1, 0, 0); + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); return 0; } #endif diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c index 945a36d..15269c6 100644 --- a/board/matrix_vision/mvblx/sys_eeprom.c +++ b/board/matrix_vision/mvblx/sys_eeprom.c @@ -326,10 +326,28 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +static inline int is_portrait(void) +{ + int i; + unsigned int orient_index = 0; /* idx of char which determines orientation */ + + for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) { + if (e.id[i] == '-') { + orient_index = i+1; + break; + } + } + + return (orient_index && + (e.id[orient_index] >= '5') && (e.id[orient_index] <= '8')); +} + int mac_read_from_eeprom(void) { u32 crc, crc_offset = offsetof(struct eeprom, crc); u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ +#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf" +#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf" if (read_eeprom()) { printf("EEPROM Read failed.\n"); @@ -374,6 +392,12 @@ int mac_read_from_eeprom(void) setenv("serial#", serial_num); } + /* decide which fpga file to load depending on orientation */ + if (is_portrait()) + setenv("fpgafilename", FILENAME_PORTRAIT); + else + setenv("fpgafilename", FILENAME_LANDSCAPE); + /* TODO should I calculate CRC here? */ return 0; } diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 4c464d1..3225c0b 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -77,7 +77,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index a507d73..3334a44 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index 4155b60..063f2cc 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 0bcf2ee..17ff94e 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index d7a2e56..99cbed4 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds index cb4a07c..adbb5f9 100644 --- a/board/mvblue/u-boot.lds +++ b/board/mvblue/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index e63a8c9..03891e9 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index 900da64..e1fe052 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index e63a8c9..03891e9 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index 900da64..e1fe052 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index e63a8c9..03891e9 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index 900da64..e1fe052 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index e63a8c9..03891e9 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index 6cbf4dc..3243fc0 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index b2fe1c5..48eb65f 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -671,7 +671,7 @@ int rx51_kp_getc(void) */ int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - omap_mmc_init(1, 0, 0); + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); return 0; } diff --git a/board/ns9750dev/config.mk b/board/ns9750dev/config.mk deleted file mode 100644 index e5d8702..0000000 --- a/board/ns9750dev/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -####################################################################### -# -# Copyright (C) 2004 by FS Forth-Systeme GmbH. -# Markus Pietrek <mpietrek@fsforth.de> -# -# @TODO -# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000 -# optionally with a ramdisk at 0080'0000 -# -# we load ourself to 0078'0000 -# -# download area is 0060'0000 -# - - -CONFIG_SYS_TEXT_BASE = 0x00780000 diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c deleted file mode 100644 index 185bc2d..0000000 --- a/board/ns9750dev/flash.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256L18T; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ns9750dev/led.c b/board/ns9750dev/led.c deleted file mode 100644 index b85c869..0000000 --- a/board/ns9750dev/led.c +++ /dev/null @@ -1,46 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Defines helper functions for toggeling LEDs - * @Usage: - * @References: [1] - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifdef CONFIG_STATUS_LED - -#include <ns9750_bbus.h> - -static inline void __led_init( led_id_t mask, int state ) -{ - XXXX; -} - -static inline void __led_toggle( led_id_t mask ) -{ -} - -static inline void __led_set( led_id_t mask, int state ) -{ -} - -#endif /* CONFIG_STATUS_LED */ diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S deleted file mode 100644 index ba5ff81..0000000 --- a/board/ns9750dev/lowlevel_init.S +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * Modified for the NS9750 DevBoard by - * (C) Copyright 2004 by FS Forth-Systeme GmbH. - * Markus Pietrek <mpietrek@fsforth.de> - * @References: [1] NS9750 Hardware Reference/December 2003 - * [2] ns9750_a.cmd from MAJIC configuration - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -#if defined(CONFIG_NS9750DEV) -# ifndef CONFIG_SKIP_LOWLEVEL_INIT -# include <./ns9750_sys.h> -# include <./ns9750_mem.h> -# endif -#endif - -/*********************************************************************** - * @Function: write_register_block - * @Return: nothing - * @Descr: Copies the register block of register_offset:register value to - * the registers at base r0. The block is assumed to start in RAM at r1 - * and end at r2. The linked RAM base address of U-Boot is assumed to be - * in r5 while the ROM base address we are running from is r6 - * Uses r3 and r4 as tempory registers - ***********************************************************************/ - -.macro write_register_block - @@ map the addresses to high memory - sub r1, r1, r5 - add r1, r1, r6 - sub r2, r2, r5 - add r2, r2, r6 - - @@ copy all -1: - @@ Write register/value pair starting at [r1] to register base r0 - ldr r3, [r1], #4 - ldr r4, [r1], #4 - str r4, [r0,r3] - cmp r1, r2 - blt 1b -.endm - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config.mk -_PHYS_FLASH: - .word PHYS_FLASH_1 @ real flash address (without mirroring) -_CAS_LATENCY: - .word 0x00022000 @ for CAS2 latency - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -.globl lowlevel_init -lowlevel_init: - - /* U-Boot may be linked to RAM at 0x780000. But this code will run in - flash from 0x0. But in order to enable RAM we have to disable the - mirror bit, therefore we have to jump to our real flash address - beginning at PHYS_FLASH_1 (CS4 Base). Therefore, - _run_at_real_flash_address may be 0x500003b0 while be linked to - 0x7803b0. So we must modify our linked addresses */ - - @@ branch to high memory address, away from 0x0 - ldr r5, _TEXT_BASE - ldr r6, _PHYS_FLASH - ldr r0, =_run_at_real_flash_address - sub r0, r0, r5 - add r0, r0, r6 - mov pc, r0 - nop @ for pipelining - -_run_at_real_flash_address: - @@ now we are running > PHYS_FLASH_1, safe to enable memory controller - - @@ Write Memory Configuration Registers - - ldr r0, _NS9750_MEM_MODULE_BASE - ldr r1, =_MEM_CONFIG_START - ldr r2, =_MEM_CONFIG_END - - write_register_block - - @@ Give SDRAM some time to settle - @@ @TODO. According to [2] it should be 2 AHB cycles. Check - - ldr r1, =0x50 -_sdram_settle: - subs r1, r1, #1 - bne _sdram_settle - -_enable_mappings: - @@ Enable SDRAM Mode - - ldr r1, =_MEM_MODE_START - ldr r2, =_MEM_MODE_END - - write_register_block - - ldr r3, _CAS_LATENCY @ perform one read from SDRAM - ldr r3, [r3] - - @@ Enable SDRAM and memory mappings - - ldr r1, =_MEM_ENABLE_START - ldr r2, =_MEM_ENABLE_END - - write_register_block - - @@ Activate AHB monitor - - ldr r0, =NS9750_SYS_MODULE_BASE - ldr r1, =_AHB_MONITOR_START - ldr r2, =_AHB_MONITOR_END - - write_register_block -_relocate_lr: - /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to - PHYS_FLASH. */ - mov r1, ip - add r1, r1, r6 - mov ip, r1 - - mov r1, lr - add r1, r1, r6 - mov lr, r1 - - @@ back to arch calling code - mov pc, lr - - .ltorg - -_NS9750_MEM_MODULE_BASE: - .word NS9750_MEM_MODULE_BASE - -_MEM_CONFIG_START: - /* Table of 2 32bit entries. First word is register address offset - relative to NS9750_MEM_MODULE_BASE, second one is value. They are - written in order of appearance */ - - @@ Register values taken from [2] - .word NS9750_MEM_CTRL - .word NS9750_MEM_CTRL_E - - .word NS9750_MEM_DYN_REFRESH - .word (0x6 & NS9750_MEM_DYN_REFRESH_MA) - - .word NS9750_MEM_DYN_READ_CFG - .word (0x1 & NS9750_MEM_DYN_READ_CFG_MA) - - .word NS9750_MEM_DYN_TRP - .word (0x1 & NS9750_MEM_DYN_TRP_MA) - - .word NS9750_MEM_DYN_TRAS - .word (0x4 & NS9750_MEM_DYN_TRAS_MA) - - .word NS9750_MEM_DYN_TAPR - .word (0x1 & NS9750_MEM_DYN_TRAS_MA) - - .word NS9750_MEM_DYN_TDAL - .word (0x5 & NS9750_MEM_DYN_TDAL_MA) - - .word NS9750_MEM_DYN_TWR - .word (0x1 & NS9750_MEM_DYN_TWR_MA) - - .word NS9750_MEM_DYN_TRC - .word (0x6 & NS9750_MEM_DYN_TRC_MA) - - .word NS9750_MEM_DYN_TRFC - .word (0x6 & NS9750_MEM_DYN_TRFC_MA) - - .word NS9750_MEM_DYN_TRRD - .word (0x1 & NS9750_MEM_DYN_TRRD_MA) - - .word NS9750_MEM_DYN_TMRD - .word (0x1 & NS9750_MEM_DYN_TMRD_MA) - - @@ CS 4 - .word NS9750_MEM_DYN_CFG(0) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(0) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 5 - .word NS9750_MEM_DYN_CFG(1) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(1) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 6 - .word NS9750_MEM_DYN_CFG(2) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(2) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 7 - .word NS9750_MEM_DYN_CFG(3) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(3) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_PALL | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) - - .word NS9750_MEM_DYN_REFRESH - .word (0x1 & NS9750_MEM_DYN_REFRESH_MA) - @@ No further register settings after refresh -_MEM_CONFIG_END: - -_MEM_MODE_START: - .word NS9750_MEM_DYN_REFRESH - .word (0x30 & NS9750_MEM_DYN_REFRESH_MA) - - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_MODE | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) -_MEM_MODE_END: - -_MEM_ENABLE_START: - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_NORMAL | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) - - @@ CS 4 - .word NS9750_MEM_DYN_CFG(0) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 5 - .word NS9750_MEM_DYN_CFG(1) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 6 - .word NS9750_MEM_DYN_CFG(2) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 7 - .word NS9750_MEM_DYN_CFG(3) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) -_MEM_ENABLE_END: - -_AHB_MONITOR_START: - .word NS9750_SYS_AHB_TIMEOUT - .word 0x01000100 @ @TODO not calculated yet - - .word NS9750_SYS_AHB_MON - .word (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \ - NS9750_SYS_AHB_MON_BATC_GEN_IRQ) -_AHB_MONITOR_END: - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c deleted file mode 100644 index fc46244..0000000 --- a/board/ns9750dev/ns9750dev.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * Markus Pietrek <mpietrek@fsforth.de> - * derived from omap1610innovator.c - * @References: [1] NS9750 Hardware Reference/December 2003 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#if defined(CONFIG_NS9750DEV) -# include <./configs/ns9750dev.h> -# include <./ns9750_bbus.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -void flash__init( void ); -void ether__init( void ); - -static inline void delay( unsigned long loops ) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - - -/*********************************************************************** - * @Function: board_init - * @Return: 0 - * @Descr: Enables BBUS modules and other devices - ***********************************************************************/ - -int board_init( void ) -{ - /* Active BBUS modules */ - *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0; - -#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new - /* arch number of OMAP 1510-Board */ - /* to be changed for OMAP 1610 Board */ - gd->bd->bi_arch_number = 234; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable(); - - flash__init(); - ether__init(); - return 0; -} - - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - -#if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif - return 0; -} diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index df4cb6b..3544b41 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2013 * NVIDIA Corporation <www.nvidia.com> * * See file CREDITS for list of people who contributed to this @@ -23,7 +23,12 @@ #include <common.h> #include <asm/arch/pinmux.h> +#include <asm/arch/gp_padctrl.h> #include "pinmux-config-cardhu.h" +#include <i2c.h> + +#define PMU_I2C_ADDRESS 0x2D +#define MAX_I2C_RETRY 3 /* * Routine: pinmux_init @@ -36,4 +41,54 @@ void pinmux_init(void) pinmux_config_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl)); +} + +#if defined(CONFIG_TEGRA_MMC) +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + uchar reg, data_buffer[1]; + int i; + + i2c_set_bus_num(0); /* PMU is on bus 0 */ + + /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */ + data_buffer[0] = 0x65; + reg = 0x32; + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + udelay(100); + } + + /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */ + data_buffer[0] = 0x09; + reg = 0x67; + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + udelay(100); + } +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO1 power rail */ + board_sdmmc_voltage_init(); } +#endif /* MMC */ diff --git a/board/nvidia/cardhu/cardhu.c.mmc b/board/nvidia/cardhu/cardhu.c.mmc deleted file mode 100644 index 9e83b6f..0000000 --- a/board/nvidia/cardhu/cardhu.c.mmc +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/pinmux.h> -#include "pinmux-config-cardhu.h" - -#include <asm/arch/clock.h> -#include <asm/arch/gp_padctrl.h> -#include <asm/arch/pmu.h> -#include <asm/arch/sdmmc.h> -#include <asm/arch-tegra/mmc.h> -#include <asm/arch-tegra/tegra_mmc.h> -#include <mmc.h> -#include <i2c.h> - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_config_table(tegra3_pinmux_common, - ARRAY_SIZE(tegra3_pinmux_common)); - - pinmux_config_table(unused_pins_lowpower, - ARRAY_SIZE(unused_pins_lowpower)); -} - -#if defined(CONFIG_MMC) -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -static void pin_mux_mmc(void) -{ -} - -/* Do I2C/PMU writes to bring up SD card bus power */ -static void board_sdmmc_voltage_init(void) -{ - uchar reg, data_buffer[1]; - int i; - - i2c_set_bus_num(0); /* PMU is on bus 0 */ - - data_buffer[0] = 0x65; - reg = 0x32; - - for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) - udelay(100); - } - - data_buffer[0] = 0x09; - reg = 0x67; - - for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) - udelay(100); - } -} - -static void pad_init_mmc(struct tegra_mmc *reg) -{ - struct apb_misc_gp_ctlr *const gpc = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg; - u32 val, offset = (unsigned int)reg; - u32 padcfg, padmask; - - debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc); - - /* Set the pad drive strength for SDMMC1 or 3 only */ - if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) { - debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", - __func__); - return; - } - - /* Set pads as per T30 TRM, section 24.6.1.2 */ - padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \ - GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN); - padmask = 0x00000FFF; - if (offset == TEGRA_SDMMC1_BASE) { - val = readl(&gpc->sdio1cfg); - val &= padmask; - val |= padcfg; - writel(val, &gpc->sdio1cfg); - } else { /* SDMMC3 */ - val = readl(&gpc->sdio3cfg); - val &= padmask; - val |= padcfg; - writel(val, &gpc->sdio3cfg); - } - - val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl); - val &= 0xFFFFFFF0; - val |= MEMCOMP_PADCTRL_VREF; - writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl); - - val = readl(&sdmmc->sdmmc_auto_cal_config); - val &= 0xFFFF0000; - val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; - writel(val, &sdmmc->sdmmc_auto_cal_config); -} - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Turn on SD-card bus power */ - board_sdmmc_voltage_init(); - - /* Set up the SDMMC pads as per the TRM */ - pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - /* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */ - tegra_mmc_init(0, 8, -1, -1); - - /* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */ - tegra_mmc_init(1, 8, -1, -1); - - return 0; -} -#endif /* MMC */ diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h index 8428bba..51d2b94 100644 --- a/board/nvidia/cardhu/pinmux-config-cardhu.h +++ b/board/nvidia/cardhu/pinmux-config-cardhu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -53,6 +53,18 @@ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ } +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ + } + static struct pingroup_config tegra3_pinmux_common[] = { /* SDMMC1 pinmux */ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), @@ -326,4 +338,9 @@ static struct pingroup_config unused_pins_lowpower[] = { DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT), }; -#endif /* _PINMUX_CONFIG_CARDHU_H_ */ +static struct padctrl_config cardhu_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_CARDHU_H_ */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index d1d8a29..7d9f361 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -46,7 +46,11 @@ #include <asm/arch/emc.h> #endif #ifdef CONFIG_USB_EHCI_TEGRA -#include <asm/arch/usb.h> +#include <asm/arch-tegra/usb.h> +#endif +#ifdef CONFIG_TEGRA_MMC +#include <asm/arch-tegra/tegra_mmc.h> +#include <asm/arch-tegra/mmc.h> #endif #include <i2c.h> #include <spi.h> @@ -221,3 +225,53 @@ int board_late_init(void) #endif return 0; } + +#if defined(CONFIG_TEGRA_MMC) +void __pin_mux_mmc(void) +{ +} + +void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc"))); + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("%s called\n", __func__); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + debug("%s: init MMC\n", __func__); + tegra_mmc_init(); + + return 0; +} + +void pad_init_mmc(struct mmc_host *host) +{ +#if defined(CONFIG_TEGRA30) + enum periph_id id = host->mmc_id; + u32 val; + + debug("%s: sdmmc address = %08x, id = %d\n", __func__, + (unsigned int)host->reg, id); + + /* Set the pad drive strength for SDMMC1 or 3 only */ + if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { + debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", + __func__); + return; + } + + val = readl(&host->reg->sdmemcmppadctl); + val &= 0xFFFFFFF0; + val |= MEMCOMP_PADCTRL_VREF; + writel(val, &host->reg->sdmemcmppadctl); + + val = readl(&host->reg->autocalcfg); + val &= 0xFFFF0000; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + writel(val, &host->reg->autocalcfg); +#endif /* T30 */ +} +#endif /* MMC */ diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index aca3c7d..2020a5f 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -24,6 +24,9 @@ */ void pinmux_init(void) { + pinmux_config_table(tegra114_pinmux_set_nontristate, + ARRAY_SIZE(tegra114_pinmux_set_nontristate)); + pinmux_config_table(tegra114_pinmux_common, ARRAY_SIZE(tegra114_pinmux_common)); diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 3dd47da..3ef6f4e 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -17,7 +17,7 @@ #ifndef _PINMUX_CONFIG_DALMORE_H_ #define _PINMUX_CONFIG_DALMORE_H_ -#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ +#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ { \ .pingroup = PINGRP_##_pingroup, \ .func = PMUX_FUNC_##_mux, \ @@ -41,7 +41,19 @@ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } -#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ +#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ { \ .pingroup = PINGRP_##_pingroup, \ .func = PMUX_FUNC_##_mux, \ @@ -50,200 +62,303 @@ .io = PMUX_PIN_##_io, \ .lock = PMUX_PIN_LOCK_##_lock, \ .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define USB_PINMUX CEC_PINMUX + +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ } static struct pingroup_config tegra114_pinmux_common[] = { + /* EXTPERIPH1 pinmux */ + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + + /* I2S0 pinmux */ + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + + /* I2S1 pinmux */ + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + + /* I2S3 pinmux */ + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + + /* CLDVFS pinmux */ + DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* VI pinmux */ + VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* VI_ALT1 pinmux */ + VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* VGP4 pinmux */ + VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* UARTD pinmux */ + DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), + + /* SPI4 pinmux */ + DEFAULT_PINMUX(GMI_AD5, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS6_N, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N, SPI4, NORMAL, NORMAL, INPUT), + + /* PWM1 pinmux */ + DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), + + /* SOC pinmux */ + DEFAULT_PINMUX(GMI_CS1_N, SOC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_OE_N, SOC, NORMAL, TRISTATE, INPUT), + + /* EXTPERIPH2 pinmux */ + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, OUTPUT), + /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_WP_N, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, NORMAL, NORMAL, OUTPUT), - - DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT), /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT), + + /* BLINK pinmux */ + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), + + /* KBC pinmux */ + DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), + + /*Audio Codec*/ + DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT), + + /* UARTA pinmux */ + DEFAULT_PINMUX(KB_ROW10, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT), + + /* I2CPWR pinmux (I2C5) */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* SYSCLK pinmux */ + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), + + /* RTCK pinmux */ + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), + + /* CLK pinmux */ + DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), + + /* PWRON pinmux */ + DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), + + /* CPU pinmux */ + DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), + + /* PMI pinmux */ + DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), + + /* RESET_OUT_N pinmux */ + DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), + + /* EXTPERIPH3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + /* UARTB pinmux */ + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), - /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + /* IRDA pinmux */ + DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), + + /* UARTC pinmux */ + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + + /* OWR pinmux */ + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + + /* CEC pinmux */ + CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), /* I2C4 pinmux */ - I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* Power I2C pinmux */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DATA1, UARTA, UP, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), - - /* KBC keys */ - DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV1, RSVD1, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS1_N, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS2_N, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT), - - /* GPIOs */ - /* SDMMC1 CD gpio */ - DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT), - - /* Touch RESET */ - DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT), - - /* Power rails GPIO */ - DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), + DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + + /* USB pinmux */ + USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* nct */ + DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT), }; static struct pingroup_config unused_pins_lowpower[] = { - DEFAULT_PINMUX(GMI_CS0_N, NAND, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS3_N, NAND, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS4_N, NAND, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(USB_VBUS_EN1, RSVD3, DOWN, TRISTATE, OUTPUT), }; -#endif /* _PINMUX_CONFIG_DALMORE_H_ */ +/* Initially setting all used GPIO's to non-TRISTATE */ +static struct pingroup_config tegra114_pinmux_set_nontristate[] = { + DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_X5_AUD, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_W3_AUD, SPI6, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X1_AUD, RSVD3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(DAP3_FS, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GPIO_PBB3, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB5, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB6, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB7, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, RSVD3, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD12, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CLK, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS0_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS3_N, GMI, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS4_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_DQS, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N, GMI, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC1_WP_N, SPI4, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW3, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK3_REQ, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), +}; +#endif /* PINMUX_CONFIG_COMMON_H */ diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index 7315577..30cf1fb 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -1,13 +1,46 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra114.dtsi" / { model = "NVIDIA Dalmore"; compatible = "nvidia,dalmore", "nvidia,tegra114"; + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; }; diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts index aeda3a1..7934e4a 100644 --- a/board/nvidia/dts/tegra20-harmony.dts +++ b/board/nvidia/dts/tegra20-harmony.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Harmony evaluation board"; @@ -9,6 +9,8 @@ aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000200"; }; memory { @@ -52,4 +54,20 @@ usb@c5004000 { nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ }; + + sdhci@c8000200 { + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 58 1>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index 527a296..c0e2e1e 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -1,7 +1,6 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "NVIDIA Seaboard"; @@ -12,14 +11,15 @@ }; aliases { - /* This defines the order of our USB ports */ + /* This defines the order of our ports */ usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; - i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -156,13 +156,16 @@ }; sdhci@c8000400 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <4>; }; sdhci@c8000600 { - support-8bit; + status = "okay"; + bus-width = <8>; }; lcd_panel: panel { diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts index 3e5e39d..e1a3d1e 100644 --- a/board/nvidia/dts/tegra20-ventana.dts +++ b/board/nvidia/dts/tegra20-ventana.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Ventana evaluation board"; @@ -8,6 +8,8 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -41,4 +43,17 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000400 { + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts index 4579557..eb92264 100644 --- a/board/nvidia/dts/tegra20-whistler.dts +++ b/board/nvidia/dts/tegra20-whistler.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Whistler evaluation board"; @@ -9,6 +9,8 @@ aliases { i2c0 = "/i2c@7000d000"; usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -57,4 +59,15 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000400 { + status = "okay"; + wp-gpios = <&gpio 173 0>; /* gpio PV5 */ + bus-width = <8>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index f9f80c5..4d22b48 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -1,7 +1,6 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; -/include/ ARCH_CPU_DTS +#include "tegra30.dtsi" / { model = "NVIDIA Cardhu"; @@ -13,6 +12,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000000"; }; memory { @@ -21,22 +22,27 @@ }; i2c@7000c000 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c400 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c500 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c700 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000d000 { + status = "okay"; clock-frequency = <100000>; }; @@ -44,4 +50,17 @@ status = "okay"; spi-max-frequency = <25000000>; }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; }; diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 93430ed..3122441 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -27,19 +27,14 @@ #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_TEGRA_MMC -#include <mmc.h> -#endif - #ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT); @@ -54,25 +49,6 @@ static void pin_mux_mmc(void) /* For CD GPIO PI5 */ pinmux_tristate_disable(PINGRP_ATC); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - debug("board_mmc_init: init SD slot J26\n"); - /* init dev 0, SD slot J26, with 8-bit bus */ - tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2); - - debug("board_mmc_init: init SD slot J5\n"); - /* init dev 2, SD slot J5, with 4-bit bus */ - tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5); - - return 0; -} #endif void pin_mux_usb(void) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 3e33da0..e581fdd 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -28,11 +28,7 @@ #include <asm/arch/funcmux.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_TEGRA_MMC -#include <mmc.h> -#endif /* TODO: Remove this code when the SPI switch is working */ #if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) @@ -51,7 +47,7 @@ void gpio_early_init_uart(void) * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT); @@ -61,25 +57,6 @@ static void pin_mux_mmc(void) /* For CD GPIO PI5 */ pinmux_tristate_disable(PINGRP_ATC); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - debug("board_mmc_init: init eMMC\n"); - /* init dev 0, eMMC chip, with 8-bit bus */ - tegra_mmc_init(0, 8, -1, -1); - - debug("board_mmc_init: init SD slot\n"); - /* init dev 1, SD slot, with 4-bit bus */ - tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5); - - return 0; -} #endif void pin_mux_usb(void) diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 592cd6b..f18aa27 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -27,32 +27,19 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> #include <i2c.h> -#ifdef CONFIG_TEGRA_MMC -#include <mmc.h> -#endif - +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) -{ - funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); -} - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) +void pin_mux_mmc(void) { uchar val; int ret; - debug("board_mmc_init called\n"); - /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ ret = i2c_set_bus_num(0); if (ret) @@ -70,17 +57,10 @@ int board_mmc_init(bd_t *bd) if (ret) printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */ - tegra_mmc_init(0, 8, -1, -1); - - /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */ - tegra_mmc_init(1, 8, -1, -1); - - return 0; + funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); } +#endif /* this is a weak define that we are overriding */ void pin_mux_usb(void) diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index 3c1c05a..a1481c8 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index 92796e6..614bbb2 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 6a6053b..9ed7718 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -23,11 +23,15 @@ */ #include <common.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/iomux-mx23.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_STATUS_LED +#include <status_led.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +46,11 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); +#ifdef CONFIG_CMD_USB + /* Enable LAN9512 */ + gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1); +#endif + return 0; } @@ -67,5 +76,9 @@ int board_init(void) /* Adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE); +#endif + return 0; } diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 7def8bc..a96c293 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -84,6 +84,10 @@ const iomux_cfg_t iomux_setup[] = { MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + /* Green LED */ + MX23_PAD_SSP1_DETECT__GPIO_2_1 | + (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL), + /* MMC 0 */ MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, @@ -91,6 +95,10 @@ const iomux_cfg_t iomux_setup[] = { MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, + + /* Ethernet */ + MX23_PAD_GPMI_ALE__GPIO_0_17 | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), }; void board_init_ll(void) diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/board/openrisc/openrisc-generic/u-boot.lds index 4cffacb..9024f30 100644 --- a/board/openrisc/openrisc-generic/u-boot.lds +++ b/board/openrisc/openrisc-generic/u-boot.lds @@ -29,7 +29,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } .rodata : { diff --git a/board/overo/overo.c b/board/overo/overo.c index fdf46a2..8690450 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -392,7 +392,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 3a62e9d..9ff5dd7 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -139,7 +139,6 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c index 4d3a1d5..6e9c3d2 100644 --- a/board/phytec/pcm051/mux.c +++ b/board/phytec/pcm051/mux.c @@ -35,7 +35,6 @@ static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ - {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index a507d73..3334a44 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 404eda0..ef3a17f 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index bb3b9de..b354409 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -80,7 +80,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds index d568312..276f525 100644 --- a/board/renesas/sh7752evb/u-boot.lds +++ b/board/renesas/sh7752evb/u-boot.lds @@ -78,7 +78,7 @@ SECTIONS PROVIDE (_egot = .); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } PROVIDE (reloc_dst_end = .); diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds index 49d6500..5882427 100644 --- a/board/renesas/sh7757lcr/u-boot.lds +++ b/board/renesas/sh7757lcr/u-boot.lds @@ -79,7 +79,7 @@ SECTIONS .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } PROVIDE (reloc_dst_end = .); diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index ec8cddd..240b936 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -100,7 +100,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds index 48ad60c..4c8baaa 100644 --- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds +++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds @@ -49,7 +49,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } >.sram . = ALIGN(4); diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds index 3bf2ae1..64c650d 100644 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ b/board/samsung/smdk6400/u-boot-nand.lds @@ -50,7 +50,7 @@ SECTIONS . = align(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = align(4); diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 7a0757f..6b99f13 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -118,7 +118,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index 07bd6fe..0b4192e 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -118,7 +118,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds index 65c1dbd..95e13c4 100644 --- a/board/sandpoint/u-boot.lds +++ b/board/sandpoint/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index ce3026f..66c5fba 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index 749980f..285e897 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index a507d73..3334a44 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index a507d73..3334a44 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index 905c91d..58f2565 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -78,7 +78,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index 4155b60..063f2cc 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds index e63a8c9..03891e9 100644 --- a/board/stx/stxxtc/u-boot.lds +++ b/board/stx/stxxtc/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug index 900da64..e1fe052 100644 --- a/board/stx/stxxtc/u-boot.lds.debug +++ b/board/stx/stxxtc/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index 5d3d8f2..99b8bfa 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -86,7 +86,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index fa0ace0..a28c704 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -147,7 +147,7 @@ int board_eth_init(bd_t *bis) !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index c516c75..d576786 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -81,6 +81,7 @@ static struct panel_config lcd_cfg[] = { .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ .panel_color = 0, + .gfx_format = GFXFORMAT_RGB24_UNPACKED, }, { .timing_h = PANEL_TIMING_H(20, 192, 4), @@ -91,6 +92,7 @@ static struct panel_config lcd_cfg[] = { .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ .panel_color = 0, + .gfx_format = GFXFORMAT_RGB24_UNPACKED, } }; #endif @@ -304,7 +306,7 @@ int board_eth_init(bd_t *bis) !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 48e6896..f4b972b 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -73,7 +73,7 @@ static inline int board_is_idk(void) return !strncmp(header.config, "SKU#02", 6); } -static int board_is_gp_evm(void) +static int __maybe_unused board_is_gp_evm(void) { return !strncmp("A33515BB", header.name, 8); } @@ -389,7 +389,8 @@ int board_late_init(void) } #endif -#ifdef CONFIG_DRIVER_TI_CPSW +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -434,26 +435,26 @@ static struct cpsw_platform_data cpsw_data = { int board_eth_init(bd_t *bis) { int rv, n = 0; -#ifdef CONFIG_DRIVER_TI_CPSW uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; - if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { - printf("<ethaddr> not set. Reading from E-fuse\n"); - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); - else - goto try_usbether; } if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { @@ -494,8 +495,11 @@ int board_eth_init(bd_t *bis) AR8051_RGMII_TX_CLK_DLY); } #endif -try_usbether: -#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_USB_ETHER) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("usbnet_devaddr", mac_addr); + rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index 888398d..0b94245 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -78,7 +78,6 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index b829a79..3d9b6dd 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -72,6 +72,7 @@ #define BBTOYS_LCD 0x03000B00 #define BCT_BRETTL3 0x01000F00 #define BCT_BRETTL4 0x02000F00 +#define LSR_COM6L_ADPT 0x01001300 #define BEAGLE_NO_EEPROM 0xffffffff DECLARE_GLOBAL_DATA_PTR; @@ -227,6 +228,14 @@ static unsigned int get_expansion_id(void) i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, sizeof(expansion_config)); + /* retry reading configuration data with 16bit addressing */ + if ((expansion_config.device_vendor == 0xFFFFFF00) || + (expansion_config.device_vendor == 0xFFFFFFFF)) { + printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n"); + i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config, + sizeof(expansion_config)); + } + i2c_set_bus_num(TWL4030_I2C_BUS); return expansion_config.device_vendor; @@ -454,6 +463,11 @@ int misc_init_r(void) case BCT_BRETTL4: printf("Recognized bct electronic GmbH brettl4 board\n"); break; + case LSR_COM6L_ADPT: + printf("Recognized LSR COM6L Adapter Board\n"); + MUX_BBTOYS_WIFI() + setenv("buddy", "lsr-com6l-adpt"); + break; case BEAGLE_NO_EEPROM: printf("No EEPROM on expansion board\n"); setenv("buddy", "none"); @@ -518,8 +532,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index c0a94a9..6d71bbc 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -544,7 +544,8 @@ static const struct panel_config dvid_cfg = { .panel_type = 0x01, /* TFT */ .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ - .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ + .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */ + .gfx_format = GFXFORMAT_RGB24_UNPACKED, }; static const struct panel_config dvid_cfg_xm = { @@ -556,6 +557,7 @@ static const struct panel_config dvid_cfg_xm = { .panel_type = 0x01, /* TFT */ .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ - .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ + .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */ + .gfx_format = GFXFORMAT_RGB24_UNPACKED, }; #endif diff --git a/board/ns9750dev/Makefile b/board/ti/dra7xx/Makefile index 0d082c5..db6da5b 100644 --- a/board/ns9750dev/Makefile +++ b/board/ti/dra7xx/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2013 +# Texas Instruments, <www.ti.com> # # See file CREDITS for list of people who contributed to this # project. @@ -12,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -25,15 +25,19 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := ns9750dev.o flash.o led.o -SOBJS := lowlevel_init.o +COBJS := evm.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c new file mode 100644 index 0000000..7bbb549 --- /dev/null +++ b/board/ti/dra7xx/evm.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated, <www.ti.com> + * + * Lokesh Vutla <lokeshvutla@ti.com> + * + * Based on previous work by: + * Aneesh V <aneesh@ti.com> + * Steve Sakoman <steve@sakoman.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl6035.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> + +#include "mux_data.h" + +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/arch/ehci.h> +#include <asm/ehci-omap.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: DRA7xx\n" +}; + +/** + * @brief board_init + * + * @return 0 + */ +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +/** + * @brief misc_init_r - Configure EVM board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ + return 0; +} + +static void do_set_mux32(u32 base, + struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h new file mode 100644 index 0000000..04c95fd --- /dev/null +++ b/board/ti/dra7xx/mux_data.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated, <www.ti.com> + * + * Sricharan R <r.sricharan@ti.com> + * Nishant Kamat <nskamat@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_DATA_DRA7XX_H_ +#define _MUX_DATA_DRA7XX_H_ + +#include <asm/arch/mux_dra7xx.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */ + {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */ + {UART1_TXD, (M0)}, /* UART1_TXD */ + {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */ + {UART1_RTSN, (M0)}, /* UART1_RTSN */ + {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */ +}; +#endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 8a3aa0c..3c2dcab 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -277,7 +277,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c index c8dfdf8..55337c0 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_evm/evm.c @@ -94,8 +94,8 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - omap_mmc_init(1, 0, 0); + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); return 0; } #endif diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 4feef78..cab0598 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -179,8 +179,7 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c index 9a1c012..052efc5 100644 --- a/board/ti/sdp3430/sdp.c +++ b/board/ti/sdp3430/sdp.c @@ -209,7 +209,6 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 982c771..4c1a4f7 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -108,8 +108,8 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - omap_mmc_init(1, 0, 0); + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); return 0; } #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index b88d978..ebff59e 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -136,8 +136,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c index e40a986..aa76f65 100644 --- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c +++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c @@ -19,7 +19,6 @@ #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/board.h> -#include <asm/arch-tegra/mmc.h> #include "../colibri_t20-common/colibri_t20-common.h" @@ -34,13 +33,13 @@ void pin_mux_usb(void) #endif #ifdef CONFIG_TEGRA_MMC -int board_mmc_init(bd_t *bd) +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); pinmux_tristate_disable(PINGRP_GMB); - - tegra_mmc_init(0, 4, -1, GPIO_PC7); - - return 0; } #endif diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts index c29b43a..c0e54af 100644 --- a/board/toradex/dts/tegra20-colibri_t20_iris.dts +++ b/board/toradex/dts/tegra20-colibri_t20_iris.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "Toradex Colibri T20"; @@ -10,6 +10,7 @@ usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; usb2 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; }; usb@c5000000 { @@ -35,4 +36,10 @@ compatible = "nand-flash"; }; }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 23 1>; /* gpio PC7 */ + bus-width = <4>; + }; }; diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index bcc618c..fbf321d 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -82,7 +82,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index cdd73fa..f25a01b 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 5d66c13..dc437d1 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -57,10 +57,6 @@ SECTIONS *(.data) } - .u_boot_list : { - #include <u-boot.lst> - } - . = ALIGN(4); .rel.dyn : { diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index 2ce5a9a..18b7752 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug index c4e5706..c02581d 100644 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ b/board/xes/xpedite1000/u-boot.lds.debug @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } |