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| author | Stefan Roese <sr@denx.de> | 2007-11-15 14:25:09 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-11-15 14:25:09 +0100 |
| commit | c9672f81f1bdb4e8ddf62aa72ca0206e8b72aa1c (patch) | |
| tree | 5d3eb5389283687a001534bd7590fb0a2833f668 /board | |
| parent | aee747f19b460a0e9da20ff21e90fdaac1cec359 (diff) | |
| download | u-boot-imx-c9672f81f1bdb4e8ddf62aa72ca0206e8b72aa1c.zip u-boot-imx-c9672f81f1bdb4e8ddf62aa72ca0206e8b72aa1c.tar.gz u-boot-imx-c9672f81f1bdb4e8ddf62aa72ca0206e8b72aa1c.tar.bz2 | |
ppc4xx: Small AMCC Kilauea cleanup
Remove not needed pci_target_init() function.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/amcc/kilauea/kilauea.c | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 0939b54..09b7382 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -289,45 +289,6 @@ int pci_pre_init(struct pci_controller * hose ) } #endif /* defined(CONFIG_PCI) */ -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*-------------------------------------------------------------------+ - * Disable everything - *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ - - /*-------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIX0_BAR0, 0 ); - - /*-------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); - - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - #ifdef CONFIG_PCI static struct pci_controller pcie_hose[2] = {{0},{0}}; |