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authorJason Liu <r64343@freescale.com>2012-02-08 16:52:28 +0800
committerJason Liu <r64343@freescale.com>2012-02-09 16:39:26 +0800
commit1a509004af6e2dd17237c6e76869408bdbaf197b (patch)
tree8bfc37af48508e23b7cc68cf9af9a5143a53e1f4 /board
parent9981c5c0e60324a46ce637b78892f96fad1e44d6 (diff)
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ENGR00174055: i.mx6dl: ddr: update ddr script to 400M_64bit_v1.1
The script we get from the following link: http://compass.freescale.net/livelink/livelink/225193471/MX6DL_init_ DDR3_400MHz_64bit_1.1.inc.txt?func=doc.Fetch&nodeid=225193471 Signed-off-by: Jason Liu <r64343@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/mx6q_arm2/flash_header.S28
1 files changed, 14 insertions, 14 deletions
diff --git a/board/freescale/mx6q_arm2/flash_header.S b/board/freescale/mx6q_arm2/flash_header.S
index d593541..cfbaae9 100644
--- a/board/freescale/mx6q_arm2/flash_header.S
+++ b/board/freescale/mx6q_arm2/flash_header.S
@@ -121,10 +121,10 @@ MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x00370037)
MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x00370037)
# DQS gating, read delay, write delay calibration values
# based on calibration compare of 0x00ffff00
-MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x41770170)
-MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x020c016d)
-MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x41770170)
-MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x02150202)
+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x422f0220)
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x021f0219)
+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x422f0220)
+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x022d022f)
MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x47494b49)
MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x48484c47)
MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x39382b2f)
@@ -143,24 +143,24 @@ MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
# MMDC init:
# in DDR3, 64-bit mode, only MMDC0 is initiated:
-MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
-MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
-MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975)
-MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
-MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x005b0e21)
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x00440e21)
MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0xc31a0000)
# Initialize 2GB DDR3 - Micron MT41J128M
# MR2
-MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
-MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803a)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
# MR3
MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
@@ -168,8 +168,8 @@ MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
# MR0
-MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
-MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038)
# ZQ calibration
MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
@@ -177,7 +177,7 @@ MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
-MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x004, 0x00011006)
MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)