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authorroy zang <tie-fei.zang@freescale.com>2007-02-28 16:46:48 +0800
committerZang Tiefei <roy@bus.ap.freescale.net>2007-02-28 16:46:48 +0800
commit00b574bdc8c54dbc9e03f63c24f62955d483e3ef (patch)
treedc49c4219bafd43c2ace6c5a3e6745d7b7264194 /board
parent30bddf2c46ab2e824f217a38db033118ac4622af (diff)
parentccbc7036648e465697ca298ba51e0e76dda352a0 (diff)
downloadu-boot-imx-00b574bdc8c54dbc9e03f63c24f62955d483e3ef.zip
u-boot-imx-00b574bdc8c54dbc9e03f63c24f62955d483e3ef.tar.gz
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Merge branch 'master' into hpc2
Conflicts: drivers/Makefile Fix the merge conflict in file drivers/Makefile Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/amcc/katmai/Makefile51
-rw-r--r--board/amcc/katmai/cmd_katmai.c267
-rw-r--r--board/amcc/katmai/config.mk38
-rw-r--r--board/amcc/katmai/init.S108
-rw-r--r--board/amcc/katmai/katmai.c514
-rw-r--r--board/amcc/katmai/katmai.h65
-rw-r--r--board/amcc/katmai/u-boot.lds141
-rw-r--r--board/cray/L1/L1.c2
-rw-r--r--board/esd/common/auto_update.c3
-rw-r--r--board/esd/cpci750/cpci750.c22
-rw-r--r--board/esd/du405/du405.c2
-rw-r--r--board/lpc2292sodimm/lpc2292sodimm.c2
-rw-r--r--board/mcc200/auto_update.c187
-rw-r--r--board/mcc200/lcd.c31
-rw-r--r--board/motionpro/Makefile50
-rw-r--r--board/motionpro/config.mk30
-rw-r--r--board/motionpro/motionpro.c172
-rw-r--r--board/motionpro/u-boot.lds123
-rw-r--r--board/mpl/common/memtst.c2
-rw-r--r--board/mpl/mip405/mip405.c5
-rw-r--r--board/prodrive/p3mx/p3mx.h1
-rw-r--r--board/sandburst/common/ppc440gx_i2c.c7
-rw-r--r--board/sandburst/common/ppc440gx_i2c.h6
-rw-r--r--board/trab/auto_update.c1
-rw-r--r--board/xilinx/ml300/Makefile2
-rw-r--r--board/xilinx/ml300/ml300.c2
-rw-r--r--board/xilinx/ml300/serial.c3
-rw-r--r--board/xilinx/xilinx_enet/emac_adapter.c2
-rw-r--r--board/xilinx/xilinx_enet/xemac.h2
-rw-r--r--board/xilinx/xilinx_enet/xemac_g.c2
-rw-r--r--board/xilinx/xilinx_iic/iic_adapter.c2
31 files changed, 1738 insertions, 107 deletions
diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile
new file mode 100644
index 0000000..d06a402
--- /dev/null
+++ b/board/amcc/katmai/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o cmd_katmai.o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c
new file mode 100644
index 0000000..684f6a5
--- /dev/null
+++ b/board/amcc/katmai/cmd_katmai.c
@@ -0,0 +1,267 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/byteorder.h>
+
+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ uchar chip;
+ ulong data;
+ int nbytes;
+ extern char console_buffer[];
+
+ char sysClock[4];
+ char cpuClock[4];
+ char plbClock[4];
+ char pcixClock[4];
+
+ if (argc < 3) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (strcmp(argv[2], "prom0") == 0)
+ chip = IIC0_BOOTPROM_ADDR;
+ else
+ chip = IIC0_ALT_BOOTPROM_ADDR;
+
+ do {
+ printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
+ nbytes = readline (" ? ");
+
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+
+ if ((strcmp(console_buffer, "33") != 0) &
+ (strcmp(console_buffer, "66") != 0))
+ nbytes=0;
+
+ strcpy(sysClock, console_buffer);
+
+ } while (nbytes == 0);
+
+ do {
+ if (strcmp(sysClock, "66") == 0) {
+ printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
+ } else {
+#ifdef CONFIG_STRESS
+ printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
+#else
+ printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
+#endif
+ }
+ nbytes = readline (" ? ");
+
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+
+ if (strcmp(sysClock, "66") == 0) {
+ if ((strcmp(console_buffer, "400") != 0) &
+ (strcmp(console_buffer, "533") != 0)
+#ifdef CONFIG_STRESS
+ & (strcmp(console_buffer, "667") != 0)
+#endif
+ ) {
+ nbytes = 0;
+ }
+ } else {
+ if ((strcmp(console_buffer, "400") != 0) &
+ (strcmp(console_buffer, "500") != 0) &
+ (strcmp(console_buffer, "533") != 0)
+#ifdef CONFIG_STRESS
+ & (strcmp(console_buffer, "667") != 0)
+#endif
+ ) {
+ nbytes = 0;
+ }
+ }
+
+ strcpy(cpuClock, console_buffer);
+
+ } while (nbytes == 0);
+
+ if (strcmp(cpuClock, "500") == 0)
+ strcpy(plbClock, "166");
+ else if (strcmp(cpuClock, "533") == 0)
+ strcpy(plbClock, "133");
+ else {
+ do {
+ if (strcmp(cpuClock, "400") == 0)
+ printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n");
+
+#ifdef CONFIG_STRESS
+ if (strcmp(cpuClock, "667") == 0)
+ printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n");
+
+#endif
+ nbytes = readline (" ? ");
+
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+
+ if (strcmp(cpuClock, "400") == 0) {
+ if ((strcmp(console_buffer, "100") != 0) &
+ (strcmp(console_buffer, "133") != 0))
+ nbytes = 0;
+ }
+#ifdef CONFIG_STRESS
+ if (strcmp(cpuClock, "667") == 0) {
+ if ((strcmp(console_buffer, "133") != 0) &
+ (strcmp(console_buffer, "166") != 0))
+ nbytes = 0;
+ }
+#endif
+ strcpy(plbClock, console_buffer);
+
+ } while (nbytes == 0);
+ }
+
+ do {
+ printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n");
+ nbytes = readline (" ? ");
+
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+
+ if ((strcmp(console_buffer, "33") != 0) &
+ (strcmp(console_buffer, "66") != 0) &
+ (strcmp(console_buffer, "100") != 0) &
+ (strcmp(console_buffer, "133") != 0)) {
+ nbytes = 0;
+ }
+ strcpy(pcixClock, console_buffer);
+
+ } while (nbytes == 0);
+
+ printf("\nsys clk = %sMhz\n", sysClock);
+ printf("cpu clk = %sMhz\n", cpuClock);
+ printf("plb clk = %sMhz\n", plbClock);
+ printf("Pci-X clk = %sMhz\n", pcixClock);
+
+ do {
+ printf("\npress [y] to write I2C bootstrap \n");
+ printf("or [n] to abort. \n");
+ printf("Don't forget to set board switches \n");
+ printf("according to your choice before re-starting \n");
+ printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
+
+ nbytes = readline (" ? ");
+ if (strcmp(console_buffer, "n") == 0)
+ return 0;
+
+ } while (nbytes == 0);
+
+ if (strcmp(sysClock, "33") == 0) {
+ if ((strcmp(cpuClock, "400") == 0) &
+ (strcmp(plbClock, "100") == 0))
+ data = 0x8678c206;
+
+ if ((strcmp(cpuClock, "400") == 0) &
+ (strcmp(plbClock, "133") == 0))
+ data = 0x8678c2c6;
+
+ if ((strcmp(cpuClock, "500") == 0))
+ data = 0x8778f2c6;
+
+ if ((strcmp(cpuClock, "533") == 0))
+ data = 0x87790252;
+
+#ifdef CONFIG_STRESS
+ if ((strcmp(cpuClock, "667") == 0) &
+ (strcmp(plbClock, "133") == 0))
+ data = 0x87794256;
+
+ if ((strcmp(cpuClock, "667") == 0) &
+ (strcmp(plbClock, "166") == 0))
+ data = 0x87794206;
+
+#endif
+ }
+ if (strcmp(sysClock, "66") == 0) {
+ if ((strcmp(cpuClock, "400") == 0) &
+ (strcmp(plbClock, "100") == 0))
+ data = 0x84706206;
+
+ if ((strcmp(cpuClock, "400") == 0) &
+ (strcmp(plbClock, "133") == 0))
+ data = 0x847062c6;
+
+ if ((strcmp(cpuClock, "533") == 0))
+ data = 0x85708206;
+
+#ifdef CONFIG_STRESS
+ if ((strcmp(cpuClock, "667") == 0) &
+ (strcmp(plbClock, "133") == 0))
+ data = 0x8570a256;
+
+ if ((strcmp(cpuClock, "667") == 0) &
+ (strcmp(plbClock, "166") == 0))
+ data = 0x8570a206;
+
+#endif
+ }
+
+#ifdef DEBUG
+ printf(" pin strap0 to write in i2c = %x\n", data);
+#endif /* DEBUG */
+
+ if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
+ printf("Error writing strap0 in %s\n", argv[2]);
+
+ if (strcmp(pcixClock, "33") == 0)
+ data = 0x00000701;
+
+ if (strcmp(pcixClock, "66") == 0)
+ data = 0x00000601;
+
+ if (strcmp(pcixClock, "100") == 0)
+ data = 0x00000501;
+
+ if (strcmp(pcixClock, "133") == 0)
+ data = 0x00000401;
+
+ if (strcmp(plbClock, "166") == 0)
+ data |= 0x05950000;
+ else
+ data |= 0x05A50000;
+
+#ifdef DEBUG
+ printf(" pin strap1 to write in i2c = %x\n", data);
+#endif /* DEBUG */
+
+ udelay(1000);
+ if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
+ printf("Error writing strap1 in %s\n", argv[2]);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ bootstrap, 3, 1, do_bootstrap,
+ "bootstrap - program the serial device strap\n",
+ "wrclk [prom0|prom1] - program the serial device strap\n"
+ );
diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk
new file mode 100644
index 0000000..115c1ae
--- /dev/null
+++ b/board/amcc/katmai/config.mk
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440SPe Evaluation (Katmai) board
+#
+
+TEXT_BASE = 0xfffc0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
new file mode 100644
index 0000000..f5900bc
--- /dev/null
+++ b/board/amcc/katmai/init.S
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+
+/**************************************************************************
+ * TLB table for revA
+ *************************************************************************/
+ .globl tlbtabA
+tlbtabA:
+ tlbtab_start
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
+
+/**************************************************************************
+ * TLB table for revB
+ *
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
+ * and ranges to be mapped for config space: it seems to only work with
+ * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
+ * set otherwise) while revA uses c_nnnn_nnnn.
+ *************************************************************************/
+ .globl tlbtabB
+tlbtabB:
+ tlbtab_start
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
new file mode 100644
index 0000000..8704925
--- /dev/null
+++ b/board/amcc/katmai/katmai.c
@@ -0,0 +1,514 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <asm-ppc/io.h>
+
+#include "katmai.h"
+#include "../cpu/ppc4xx/440spe_pcie.h"
+
+#undef PCIE_ENDPOINT
+/* #define PCIE_ENDPOINT 1 */
+
+int ppc440spe_init_pcie_rootport(int port);
+void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
+
+int board_early_init_f (void)
+{
+ unsigned long mfr;
+ unsigned long pfc;
+
+ /*----------------------------------------------------------------------+
+ * Interrupt controller setup for the Katmai 440SPe Evaluation board.
+ *-----------------------------------------------------------------------+
+ *-----------------------------------------------------------------------+
+ * Interrupt | Source | Pol. | Sensi.| Crit. |
+ *-----------+-----------------------------------+-------+-------+-------+
+ * IRQ 00 | UART0 | High | Level | Non |
+ * IRQ 01 | UART1 | High | Level | Non |
+ * IRQ 02 | IIC0 | High | Level | Non |
+ * IRQ 03 | IIC1 | High | Level | Non |
+ * IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
+ * IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
+ * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
+ * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
+ * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
+ * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
+ * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
+ * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
+ * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
+ * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
+ * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
+ * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
+ * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
+ * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
+ * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
+ * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
+ * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
+ * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ * IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
+ * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
+ * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
+ * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
+ * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
+ * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
+ * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
+ * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
+ * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
+ *------------------------------------------------------------------------
+ * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
+ * IRQ 33 | MAL Serr | High | Level | Non |
+ * IRQ 34 | MAL Txde | High | Level | Non |
+ * IRQ 35 | MAL Rxde | High | Level | Non |
+ * IRQ 36 | DMC CE or DMC UE | High | Level | Non |
+ * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
+ * IRQ 38 | MAL TX EOB | High | Level | Non |
+ * IRQ 39 | MAL RX EOB | High | Level | Non |
+ * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
+ * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
+ * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
+ * IRQ 43 | L2 Cache | Risin | Edge | Non |
+ * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
+ * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
+ * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
+ * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
+ * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
+ * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
+ * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
+ * IRQ 54 | DMA Error | High | Level | Non |
+ * IRQ 55 | DMA I2O Error | High | Level | Non |
+ * IRQ 56 | Serial ROM | High | Level | Non |
+ * IRQ 57 | PCIX0 Error | High | Edge | Non |
+ * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
+ * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
+ * IRQ 60 | EMAC0 Interrupt | High | Level | Non |
+ * IRQ 61 | EMAC0 Wake-up | High | Level | Non |
+ * IRQ 62 | Reserved | High | Level | Non |
+ * IRQ 63 | XOR | High | Level | Non |
+ *-----------------------------------------------------------------------
+ * IRQ 64 | PE0 AL | High | Level | Non |
+ * IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ * IRQ 68 | PE0 TCR | High | Level | Non |
+ * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ * IRQ 70 | PE0 DCR Error | High | Level | Non |
+ * IRQ 71 | Reserved | N/A | N/A | Non |
+ * IRQ 72 | PE1 AL | High | Level | Non |
+ * IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ * IRQ 76 | PE1 TCR | High | Level | Non |
+ * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ * IRQ 78 | PE1 DCR Error | High | Level | Non |
+ * IRQ 79 | Reserved | N/A | N/A | Non |
+ * IRQ 80 | PE2 AL | High | Level | Non |
+ * IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ * IRQ 84 | PE2 TCR | High | Level | Non |
+ * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ * IRQ 86 | PE2 DCR Error | High | Level | Non |
+ * IRQ 87 | Reserved | N/A | N/A | Non |
+ * IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ * IRQ 94 | Reserved | N/A | N/A | Non |
+ * IRQ 95 | Reserved | N/A | N/A | Non |
+ *-----------------------------------------------------------------------
+ * IRQ 96 | PE0 INTA | High | Level | Non |
+ * IRQ 97 | PE0 INTB | High | Level | Non |
+ * IRQ 98 | PE0 INTC | High | Level | Non |
+ * IRQ 99 | PE0 INTD | High | Level | Non |
+ * IRQ 100 | PE1 INTA | High | Level | Non |
+ * IRQ 101 | PE1 INTB | High | Level | Non |
+ * IRQ 102 | PE1 INTC | High | Level | Non |
+ * IRQ 103 | PE1 INTD | High | Level | Non |
+ * IRQ 104 | PE2 INTA | High | Level | Non |
+ * IRQ 105 | PE2 INTB | High | Level | Non |
+ * IRQ 106 | PE2 INTC | High | Level | Non |
+ * IRQ 107 | PE2 INTD | Risin | Edge | Non |
+ * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
+ * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
+ * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
+ * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
+ * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
+ * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
+ * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
+ * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
+ * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
+ * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
+ * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
+ * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
+ * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
+ * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
+ * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
+ * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
+ * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
+ * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
+ * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
+ * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
+ *-----------+-----------------------------------+-------+-------+-------+ */
+ /*-------------------------------------------------------------------------+
+ * Put UICs in PowerPC440SPemode.
+ * Initialise UIC registers. Clear all interrupts. Disable all interrupts.
+ * Set critical interrupt values. Set interrupt polarities. Set interrupt
+ * trigger levels. Make bit 0 High priority. Clear all interrupts again.
+ *------------------------------------------------------------------------*/
+ mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic3er, 0x00000000); /* disable all interrupts */
+ mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
+ mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
+ mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
+ mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
+
+
+ mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
+ mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
+ mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
+ mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
+ mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
+ mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
+ mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
+ mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
+ mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
+ mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
+
+ mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
+ mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
+ mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
+ mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
+ mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
+ mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
+ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
+
+/* SDR0_MFR should be part of Ethernet init */
+ mfsdr (sdr_mfr, mfr);
+ mfr &= ~SDR0_MFR_ECS_MASK;
+/* mtsdr(sdr_mfr, mfr); */
+
+ /*
+ * Setup GPIO signalling per defines in katmai.h
+ */
+ pfc = PFC0_KATMAI;
+ mtsdr(SDR0_PFC0, pfc);
+
+ out32(GPIO0_OR_ADDR, GPIO_OR_KATMAI);
+ out32(GPIO0_ODR_ADDR, GPIO_ODR_KATMAI);
+ out32(GPIO0_TCR_ADDR, GPIO_TCR_KATMAI);
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Katmai - AMCC 440SPe Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) 0x00000000;
+ uint *pend = (uint *) 0x08000000;
+ uint *p;
+
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+ return 0;
+}
+#endif
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+ unsigned long strap;
+
+ /*-------------------------------------------------------------------+
+ * The katmai board is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *-------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
+ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*-------------------------------------------------------------------+
+ * Disable everything
+ *-------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0SA, 0 ); /* disable */
+ out32r( PCIX0_PIM1SA, 0 ); /* disable */
+ out32r( PCIX0_PIM2SA, 0 ); /* disable */
+ out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+ /*-------------------------------------------------------------------+
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+ * strapping options to not support sizes such as 128/256 MB.
+ *-------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAH, 0 );
+ out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r( PCIX0_BAR0, 0 );
+
+ /*-------------------------------------------------------------------+
+ * Program the board's subsystem id/vendor id
+ *-------------------------------------------------------------------*/
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+ out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI)
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+int is_pci_host(struct pci_controller *hose)
+{
+ /* The katmai board is always configured as host. */
+ return 1;
+}
+
+static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
+
+void pcie_setup_hoses(void)
+{
+ struct pci_controller *hose;
+ int i, bus;
+
+ /*
+ * assume we're called after the PCIX hose is initialized, which takes
+ * bus ID 0 and therefore start numbering PCIe's from 1.
+ */
+ bus = 1;
+ for (i = 0; i <= 2; i++) {
+#ifdef PCIE_ENDPOINT
+ if (ppc440spe_init_pcie_endport(i)) {
+#else
+ if (ppc440spe_init_pcie_rootport(i)) {
+#endif
+ printf("PCIE%d: initialization failed\n", i);
+ continue;
+ }
+
+ hose = &pcie_hose[i];
+ hose->first_busno = bus;
+ hose->last_busno = bus;
+ bus++;
+
+ /* setup mem resource */
+ pci_set_region(hose->regions + 0,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMSIZE,
+ PCI_REGION_MEM
+ );
+ hose->region_count = 1;
+ pci_register_hose(hose);
+
+#ifdef PCIE_ENDPOINT
+ ppc440spe_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+#else
+ ppc440spe_setup_pcie_rootpoint(hose, i);
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+#endif
+ }
+}
+#endif /* defined(CONFIG_PCI) */
+
+int misc_init_f (void)
+{
+ uint reg;
+#if defined(CONFIG_STRESS)
+ uint i ;
+ uint disp;
+#endif
+
+ /* minimal init for PCIe */
+#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
+ /* pci express 0 Endpoint Mode */
+ mfsdr(SDR0_PE0DLPSET, reg);
+ reg &= (~0x00400000);
+ mtsdr(SDR0_PE0DLPSET, reg);
+#else
+ /* pci express 0 Rootpoint Mode */
+ mfsdr(SDR0_PE0DLPSET, reg);
+ reg |= 0x00400000;
+ mtsdr(SDR0_PE0DLPSET, reg);
+#endif
+ /* pci express 1 Rootpoint Mode */
+ mfsdr(SDR0_PE1DLPSET, reg);
+ reg |= 0x00400000;
+ mtsdr(SDR0_PE1DLPSET, reg);
+ /* pci express 2 Rootpoint Mode */
+ mfsdr(SDR0_PE2DLPSET, reg);
+ reg |= 0x00400000;
+ mtsdr(SDR0_PE2DLPSET, reg);
+
+#if defined(CONFIG_STRESS)
+ /*
+ * All this setting done by linux only needed by stress an charac. test
+ * procedure
+ * PCIe 1 Rootpoint PCIe2 Endpoint
+ * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
+ */
+ for (i=0,disp=0; i<8; i++,disp+=3) {
+ mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
+ reg |= 0x33000000;
+ mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
+ }
+
+ /*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
+ for (i=0,disp=0; i<4; i++,disp+=3) {
+ mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
+ reg |= 0x33000000;
+ mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
+ }
+
+ /*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
+ for (i=0,disp=0; i<4; i++,disp+=3) {
+ mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
+ reg |= 0x33000000;
+ mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
+ }
+
+ reg = 0x21242222;
+ mtsdr(SDR0_PE2UTLSET1, reg);
+ reg = 0x11000000;
+ mtsdr(SDR0_PE2UTLSET2, reg);
+ /* pci express 1 Endpoint Mode */
+ reg = 0x00004000;
+ mtsdr(SDR0_PE2DLPSET, reg);
+
+ mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return (ctrlc());
+}
+#endif
diff --git a/board/amcc/katmai/katmai.h b/board/amcc/katmai/katmai.h
new file mode 100644
index 0000000..9d5b793
--- /dev/null
+++ b/board/amcc/katmai/katmai.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KATMAI_H_
+#define __KATMAI_H_
+
+/*----------------------------------------------------------------------------
+ * XX
+ * XXXX XX XXX XXX XXXX
+ * XX XX XX XX XX XX
+ * XX XXX XX XX XX XX XX
+ * XX XX XXXXX XX XX XX
+ * XXXX XX XXXX XXXX
+ * XXXX
+ *
+ * The 440SPe provices 32 bits of GPIO. By default all GPIO pins
+ * are disabled, and must be explicitly enabled by setting a
+ * bit in the SDR0_PFC0 indirect DCR. Each GPIO maps 1-to-1 with the
+ * corresponding bit in the SDR0_PFC0 register (note that bit numbers
+ * reflect the PowerPC convention where bit 0 is the most-significant
+ * bit).
+ *
+ * Katmai specific:
+ * RS232_RX_EN# is held HIGH during reset by hardware, keeping the
+ * RS232_CTS, DSR & DCD signals coming from the MAX3411 (U26) in
+ * Hi-Z condition. This prevents contention between the MAX3411 (U26)
+ * and 74CBTLV3125PG (U2) during reset.
+ *
+ * RS232_RX_EN# is connected as GPIO pin 30. Once the processor
+ * is released from reset, this pin must be configured as an output and
+ * then driven high to enable the receive signals from the UART transciever.
+ *----------------------------------------------------------------------------*/
+#define GPIO_ENABLE(gpio) (0x80000000 >> (gpio))
+
+#define PFC0_KATMAI GPIO_ENABLE(30)
+#define GPIO_OR_KATMAI GPIO_ENABLE(30) /* Drive all outputs low except GPIO 30 */
+#define GPIO_TCR_KATMAI GPIO_ENABLE(30)
+#define GPIO_ODR_KATMAI 0 /* Disable open drain for all outputs */
+
+#define GPIO0_OR_ADDR (CFG_PERIPHERAL_BASE + 0x700)
+#define GPIO0_TCR_ADDR (CFG_PERIPHERAL_BASE + 0x704)
+#define GPIO0_ODR_ADDR (CFG_PERIPHERAL_BASE + 0x718)
+#define GPIO0_IR_ADDR (CFG_PERIPHERAL_BASE + 0x71C)
+
+#endif /* __KATMAI_H_ */
diff --git a/board/amcc/katmai/u-boot.lds b/board/amcc/katmai/u-boot.lds
new file mode 100644
index 0000000..bf8fc5d
--- /dev/null
+++ b/board/amcc/katmai/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/katmai/init.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index a7114eb..a0fac7f 100644
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <asm/processor.h>
-#include <405gp_i2c.h>
+#include <4xx_i2c.h>
#include <command.h>
#include <rtc.h>
#include <post.h>
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index 5cd3423..001fd68 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -33,6 +33,7 @@
#include <asm/byteorder.h>
#include <linux/mtd/nand_legacy.h>
#include <fat.h>
+#include <part.h>
#include "auto_update.h"
@@ -71,8 +72,6 @@ extern int transfer_pic(unsigned char, unsigned char *, int, int);
extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
extern int flash_write (char *, ulong, ulong);
-/* change char* to void* to shutup the compiler */
-extern block_dev_desc_t *get_dev (char*, int);
#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
/* references to names in cmd_nand.c */
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 36bb7ce..17e3568 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -366,12 +366,12 @@ int misc_init_r ()
dcache_lock ();
#endif
if (flash_info[3].size < CFG_FLASH_INCREMENT) {
- unsigned int flash_offset;
+ unsigned int flash_offset;
unsigned int l;
flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size;
for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
- if (flash_info[3].start[l] != 0) {
+ if (flash_info[3].start[l] != 0) {
flash_info[3].start[l] += flash_offset;
}
}
@@ -503,7 +503,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
{
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0"); /* Clobbers fr0 */
+ : : : "fr0"); /* Clobbers fr0 */
return;
}
@@ -581,9 +581,9 @@ int mem_test_data (void)
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
- /* hi = (temp64>>32) & 0xffffffff; */
- /* lo = temp64 & 0xffffffff; */
- /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+ /* hi = (temp64>>32) & 0xffffffff; */
+ /* lo = temp64 & 0xffffffff; */
+ /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
@@ -856,11 +856,11 @@ int testdram (void)
}
#endif /* CFG_DRAM_TEST */
-/* ronen - the below functions are used by the bootm function */
+/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
-/* the kernel data areas. */
-/* - we diable and invalidate the icache and dcache. */
+/* the kernel data areas. */
+/* - we diable and invalidate the icache and dcache. */
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
{
u32 temp;
@@ -911,13 +911,11 @@ int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
GT_REG_READ(0x3d4, &reset_sample_high);
printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
- return(0);
+ return(0);
}
-
U_BOOT_CMD(
show_cfg, 1, 1, do_show_cfg,
"show_cfg- Show Marvell strapping register\n",
"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
);
-
diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index a019ce4..6943213 100644
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -25,7 +25,7 @@
#include "du405.h"
#include <asm/processor.h>
#include <ppc4xx.h>
-#include <405gp_i2c.h>
+#include <4xx_i2c.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/lpc2292sodimm/lpc2292sodimm.c b/board/lpc2292sodimm/lpc2292sodimm.c
index de04c66..d212c63 100644
--- a/board/lpc2292sodimm/lpc2292sodimm.c
+++ b/board/lpc2292sodimm/lpc2292sodimm.c
@@ -46,7 +46,7 @@ int board_init (void)
gd->bd->bi_arch_number = 83;
/* location of boot parameters */
- gd->bd->bi_boot_params = 0xc0000100;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c
index f1bb721..90d03ec 100644
--- a/board/mcc200/auto_update.c
+++ b/board/mcc200/auto_update.c
@@ -23,6 +23,7 @@
#include <image.h>
#include <asm/byteorder.h>
#include <usb.h>
+#include <part.h>
#ifdef CFG_HUSH_PARSER
#include <hush.h>
@@ -47,25 +48,6 @@
#error "must define CFG_CMD_FAT"
#endif
-/*
- * Check whether a USB memory stick is plugged in.
- * If one is found:
- * 1) if prepare.img ist found load it into memory. If it is
- * valid then run it.
- * 2) if preinst.img is found load it into memory. If it is
- * valid then run it. Update the EEPROM.
- * 3) if firmw_01.img is found load it into memory. If it is valid,
- * burn it into FLASH and update the EEPROM.
- * 4) if kernl_01.img is found load it into memory. If it is valid,
- * burn it into FLASH and update the EEPROM.
- * 5) if app.img is found load it into memory. If it is valid,
- * burn it into FLASH and update the EEPROM.
- * 6) if disk.img is found load it into memory. If it is valid,
- * burn it into FLASH and update the EEPROM.
- * 7) if postinst.img is found load it into memory. If it is
- * valid then run it. Update the EEPROM.
- */
-
#undef AU_DEBUG
#undef debug
@@ -78,6 +60,7 @@
/* possible names of files on the USB stick. */
#define AU_FIRMWARE "u-boot.img"
#define AU_KERNEL "kernel.img"
+#define AU_ROOTFS "rootfs.img"
struct flash_layout {
long start;
@@ -89,33 +72,47 @@ struct flash_layout {
#define AU_FL_FIRMWARE_ND 0xfC03FFFF
#define AU_FL_KERNEL_ST 0xfC0C0000
#define AU_FL_KERNEL_ND 0xfC1BFFFF
+#define AU_FL_ROOTFS_ST 0xFC1C0000
+#define AU_FL_ROOTFS_ND 0xFCFBFFFF
static int au_usb_stor_curr_dev; /* current device */
/* index of each file in the following arrays */
#define IDX_FIRMWARE 0
#define IDX_KERNEL 1
+#define IDX_ROOTFS 2
/* max. number of files which could interest us */
-#define AU_MAXFILES 2
+#define AU_MAXFILES 3
/* pointers to file names */
-char *aufile[AU_MAXFILES];
+char *aufile[AU_MAXFILES] = {
+ AU_FIRMWARE,
+ AU_KERNEL,
+ AU_ROOTFS
+};
/* sizes of flash areas for each file */
-long ausize[AU_MAXFILES];
+long ausize[AU_MAXFILES] = {
+ (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST,
+ (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST,
+ (AU_FL_ROOTFS_ND + 1) - AU_FL_ROOTFS_ST,
+};
/* array of flash areas start and end addresses */
-struct flash_layout aufl_layout[AU_MAXFILES] = { \
- {AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \
- {AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \
+struct flash_layout aufl_layout[AU_MAXFILES] = {
+ { AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND, },
+ { AU_FL_KERNEL_ST, AU_FL_KERNEL_ND, },
+ { AU_FL_ROOTFS_ST, AU_FL_ROOTFS_ND, },
};
+ulong totsize;
+
/* where to load files into memory */
#define LOAD_ADDR ((unsigned char *)0x00200000)
-/* the app is the largest image */
-#define MAX_LOADSZ ausize[IDX_KERNEL]
+/* the root file system is the largest image */
+#define MAX_LOADSZ ausize[IDX_ROOTFS]
/*i2c address of the keypad status*/
#define I2C_PSOC_KEYPAD_ADDR 0x53
@@ -134,9 +131,12 @@ extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
extern int flash_sect_erase(ulong, ulong);
extern int flash_sect_protect (int, ulong, ulong);
extern int flash_write (char *, ulong, ulong);
-/* change char* to void* to shutup the compiler */
-extern block_dev_desc_t *get_dev (char*, int);
extern int u_boot_hush_start(void);
+#ifdef CONFIG_PROGRESSBAR
+extern void show_progress(int, int);
+extern void lcd_puts (char *);
+extern void lcd_enable(void);
+#endif
int au_check_cksum_valid(int idx, long nbytes)
{
@@ -162,8 +162,7 @@ int au_check_cksum_valid(int idx, long nbytes)
int au_check_header_valid(int idx, long nbytes)
{
image_header_t *hdr;
- unsigned long checksum;
- unsigned char buf[4];
+ unsigned long checksum, fsize;
hdr = (image_header_t *)LOAD_ADDR;
/* check the easy ones first */
@@ -176,10 +175,12 @@ int au_check_header_valid(int idx, long nbytes)
#endif
if (nbytes < sizeof(*hdr)) {
printf ("Image %s bad header SIZE\n", aufile[idx]);
+ ausize[idx] = 0;
return -1;
}
if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) {
printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
+ ausize[idx] = 0;
return -1;
}
/* check the hdr CRC */
@@ -188,30 +189,46 @@ int au_check_header_valid(int idx, long nbytes)
if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) {
printf ("Image %s bad header checksum\n", aufile[idx]);
+ ausize[idx] = 0;
return -1;
}
hdr->ih_hcrc = htonl(checksum);
/* check the type - could do this all in one gigantic if() */
if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
printf ("Image %s wrong type\n", aufile[idx]);
+ ausize[idx] = 0;
return -1;
}
if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) {
printf ("Image %s wrong type\n", aufile[idx]);
+ ausize[idx] = 0;
+ return -1;
+ }
+ if ((idx == IDX_ROOTFS) &&
+ ( (hdr->ih_type != IH_TYPE_RAMDISK) && (hdr->ih_type != IH_TYPE_FILESYSTEM) )
+ ) {
+ printf ("Image %s wrong type\n", aufile[idx]);
+ ausize[idx] = 0;
return -1;
}
/* recycle checksum */
checksum = ntohl(hdr->ih_size);
- /* for kernel and app the image header must also fit into flash */
- if (idx != IDX_FIRMWARE)
+
+ fsize = checksum + sizeof(*hdr);
+ /* for kernel and ramdisk the image header must also fit into flash */
+ if (idx == IDX_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK)
checksum += sizeof(*hdr);
+
/* check the size does not exceed space in flash. HUSH scripts */
- /* all have ausize[] set to 0 */
if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
printf ("Image %s is bigger than FLASH\n", aufile[idx]);
+ ausize[idx] = 0;
return -1;
}
- return 0;
+ /* Update with the real filesize */
+ ausize[idx] = fsize;
+
+ return checksum; /* return size to be written to flash */
}
int au_do_update(int idx, long sz)
@@ -256,8 +273,12 @@ int au_do_update(int idx, long sz)
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
flash_sect_erase(start, end);
wait_ms(100);
+#ifdef CONFIG_PROGRESSBAR
+ show_progress(end - start, totsize);
+#endif
+
/* strip the header - except for the kernel and ramdisk */
- if (hdr->ih_type == IH_TYPE_KERNEL) {
+ if (hdr->ih_type == IH_TYPE_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK) {
addr = (char *)hdr;
off = sizeof(*hdr);
nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
@@ -280,9 +301,13 @@ int au_do_update(int idx, long sz)
return -1;
}
- /* check the dcrc of the copy */
+#ifdef CONFIG_PROGRESSBAR
+ show_progress(nbytes, totsize);
+#endif
+
+ /* check the data CRC of the copy */
if (crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) {
- printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]);
+ printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]);
return -1;
}
@@ -302,10 +327,10 @@ int do_auto_update(void)
{
block_dev_desc_t *stor_dev;
long sz;
- int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+ int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc;
char *env;
long start, end;
- char keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
+ uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
/*
* Read keypad status
@@ -317,14 +342,11 @@ int do_auto_update(void)
/*
* Check keypad
*/
- if ( !(keypad_status1[0] & KEYPAD_MASK_HI) ||
- (keypad_status1[0] != keypad_status2[0])) {
- return 0;
- }
if ( !(keypad_status1[1] & KEYPAD_MASK_LO) ||
(keypad_status1[1] != keypad_status2[1])) {
return 0;
}
+
au_usb_stor_curr_dev = -1;
/* start USB */
if (usb_stop() < 0) {
@@ -359,14 +381,6 @@ int do_auto_update(void)
debug ("file_fat_detectfs failed\n");
}
- /* initialize the array of file names */
- memset(aufile, 0, sizeof(aufile));
- aufile[IDX_FIRMWARE] = AU_FIRMWARE;
- aufile[IDX_KERNEL] = AU_KERNEL;
- /* initialize the array of flash sizes */
- memset(ausize, 0, sizeof(ausize));
- ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST;
- ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST;
/*
* now check whether start and end are defined using environment
* variables.
@@ -381,8 +395,8 @@ int do_auto_update(void)
end = simple_strtoul(env, NULL, 16);
if (start >= 0 && end && end > start) {
ausize[IDX_FIRMWARE] = (end + 1) - start;
- aufl_layout[0].start = start;
- aufl_layout[0].end = end;
+ aufl_layout[IDX_FIRMWARE].start = start;
+ aufl_layout[IDX_FIRMWARE].end = end;
}
start = -1;
end = 0;
@@ -394,32 +408,73 @@ int do_auto_update(void)
end = simple_strtoul(env, NULL, 16);
if (start >= 0 && end && end > start) {
ausize[IDX_KERNEL] = (end + 1) - start;
- aufl_layout[1].start = start;
- aufl_layout[1].end = end;
+ aufl_layout[IDX_KERNEL].start = start;
+ aufl_layout[IDX_KERNEL].end = end;
}
+ start = -1;
+ end = 0;
+ env = getenv("rootfs_st");
+ if (env != NULL)
+ start = simple_strtoul(env, NULL, 16);
+ env = getenv("rootfs_nd");
+ if (env != NULL)
+ end = simple_strtoul(env, NULL, 16);
+ if (start >= 0 && end && end > start) {
+ ausize[IDX_ROOTFS] = (end + 1) - start;
+ aufl_layout[IDX_ROOTFS].start = start;
+ aufl_layout[IDX_ROOTFS].end = end;
+ }
+
/* make certain that HUSH is runnable */
u_boot_hush_start();
/* make sure that we see CTRL-C and save the old state */
old_ctrlc = disable_ctrlc(0);
bitmap_first = 0;
- /* just loop thru all the possible files */
+
+ /* validate the images first */
for (i = 0; i < AU_MAXFILES; i++) {
+ ulong imsize;
/* just read the header */
sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t));
debug ("read %s sz %ld hdr %d\n",
aufile[i], sz, sizeof(image_header_t));
if (sz <= 0 || sz < sizeof(image_header_t)) {
debug ("%s not found\n", aufile[i]);
+ ausize[i] = 0;
continue;
}
- if (au_check_header_valid(i, sz) < 0) {
+ /* au_check_header_valid() updates ausize[] */
+ if ((imsize = au_check_header_valid(i, sz)) < 0) {
debug ("%s header not valid\n", aufile[i]);
continue;
}
- sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
+ /* totsize accounts for image size and flash erase size */
+ totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start));
+ }
+
+#ifdef CONFIG_PROGRESSBAR
+ if (totsize) {
+ lcd_puts(" Update in progress\n");
+ lcd_enable();
+ }
+#endif
+
+ /* just loop thru all the possible files */
+ for (i = 0; i < AU_MAXFILES && totsize; i++) {
+ if (!ausize[i]) {
+ continue;
+ }
+ sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]);
+
debug ("read %s sz %ld hdr %d\n",
aufile[i], sz, sizeof(image_header_t));
+
+ if (sz != ausize[i]) {
+ printf ("%s: size %d read %d?\n", aufile[i], ausize[i], sz);
+ continue;
+ }
+
if (sz <= 0 || sz <= sizeof(image_header_t)) {
debug ("%s not found\n", aufile[i]);
continue;
@@ -443,8 +498,8 @@ int do_auto_update(void)
}
cnt++;
#ifdef AU_TEST_ONLY
- } while (res < 0 && cnt < 3);
- if (cnt < 3)
+ } while (res < 0 && cnt < (AU_MAXFILES + 1));
+ if (cnt < (AU_MAXFILES + 1))
#else
} while (res < 0);
#endif
@@ -452,6 +507,16 @@ int do_auto_update(void)
usb_stop();
/* restore the old state */
disable_ctrlc(old_ctrlc);
+#ifdef CONFIG_PROGRESSBAR
+ if (totsize) {
+ if (!res) {
+ lcd_puts("\n Update completed\n");
+ } else {
+ lcd_puts("\n Update error\n");
+ }
+ lcd_enable();
+ }
+#endif
return 0;
}
#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c
index b262516..98b86d1 100644
--- a/board/mcc200/lcd.c
+++ b/board/mcc200/lcd.c
@@ -24,13 +24,13 @@
#ifdef CONFIG_LCD
-#define SWAPPED_LCD
+#undef SWAPPED_LCD /* For the previous h/w version */
/*
* The name of the device used for communication
* with the PSoC.
*/
#define PSOC_PSC MPC5XXX_PSC2
-#define PSOC_BAUD 500000UL
+#define PSOC_BAUD 230400UL
#define RTS_ASSERT 1
#define RTS_NEGATE 0
@@ -181,10 +181,35 @@ void lcd_enable (void)
udelay (PSOC_WAIT_TIME);
}
if (!retries) {
- printf ("%s Error: PSoC doesn't respond on "
+ printf ("%s Warning: PSoC doesn't respond on "
"RTS NEGATE\n", __FUNCTION__);
}
return;
}
+#ifdef CONFIG_PROGRESSBAR
+
+#define FONT_WIDTH 8 /* the same as VIDEO_FONT_WIDTH in video_font.h */
+void show_progress (int size, int tot)
+{
+ int cnt;
+ int i;
+ static int rc = 0;
+
+ rc += size;
+
+ cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot;
+
+ rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH);
+
+ for (i = 0; i < cnt; i++) {
+ lcd_putc(0xdc);
+ }
+
+ if (cnt) {
+ lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */
+ }
+}
+
+#endif
#endif /* CONFIG_LCD */
diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile
new file mode 100644
index 0000000..698ead1
--- /dev/null
+++ b/board/motionpro/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/motionpro/config.mk b/board/motionpro/config.mk
new file mode 100644
index 0000000..e7934d2
--- /dev/null
+++ b/board/motionpro/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2006-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Promess Motion-PRO
+#
+
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
new file mode 100644
index 0000000..d60d233
--- /dev/null
+++ b/board/motionpro/motionpro.c
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
+ * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
+ * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
+ * Also changed the refresh for 100Mhz operation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+
+/* Kollmorgen DPR initialization data */
+struct init_elem {
+ unsigned long addr;
+ unsigned len;
+ char *data;
+ } init_seq[] = {
+ {0x500003F2, 2, "\x86\x00"}, /* HW parameter */
+ {0x500003F0, 2, "\x00\x00"},
+ {0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */
+ };
+
+/*
+ * Initialize Kollmorgen DPR
+ */
+static void kollmorgen_init(void)
+{
+ unsigned i, j;
+ vu_char *p;
+
+ for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
+ p = (vu_char *)init_seq[i].addr;
+ for (j = 0; j < init_seq[i].len; ++j)
+ *(p + j) = *(init_seq[i].data + j);
+ }
+
+ printf("DPR: Kollmorgen DPR initialized\n");
+}
+
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+ /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
+ *(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
+
+ /* Initialize Kollmorgen DPR */
+ kollmorgen_init();
+
+ return 0;
+}
+
+
+#ifndef CFG_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+ hi_addr_bit;
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+ hi_addr_bit;
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+ hi_addr_bit;
+
+ /* auto refresh, second time */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+ hi_addr_bit;
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+}
+#endif /* !CFG_RAMBOOT */
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+long int initdram (int board_type)
+{
+ ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+ ulong test1, test2;
+
+ /* configure SDRAM start/end for detection */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+ sdram_start(0);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 and disable it */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
+
+#else /* !CFG_RAMBOOT */
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+#endif /* CFG_RAMBOOT */
+
+ /* return total ram size */
+ return dramsize;
+}
+
+
+int checkboard (void)
+{
+ puts("Board: Promess Motion-PRO board\n");
+ return 0;
+}
diff --git a/board/motionpro/u-boot.lds b/board/motionpro/u-boot.lds
new file mode 100644
index 0000000..8fa9c0f
--- /dev/null
+++ b/board/motionpro/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc5xxx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c
index ff1190a..1d28513 100644
--- a/board/mpl/common/memtst.c
+++ b/board/mpl/common/memtst.c
@@ -48,7 +48,7 @@ int testdram (void)
#include <common.h>
#include <asm/processor.h>
-#include <405gp_i2c.h>
+#include <4xx_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 34f3289..4b1c1c0 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -65,7 +65,7 @@
#include <common.h>
#include "mip405.h"
#include <asm/processor.h>
-#include <405gp_i2c.h>
+#include <4xx_i2c.h>
#include <miiphy.h>
#include "../common/common_util.h"
#include <i2c.h>
@@ -73,9 +73,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern block_dev_desc_t * scsi_get_dev(int dev);
-extern block_dev_desc_t * ide_get_dev(int dev);
-
#undef SDRAM_DEBUG
#define ENABLE_ECC /* for ecc boards */
#define FALSE 0
diff --git a/board/prodrive/p3mx/p3mx.h b/board/prodrive/p3mx/p3mx.h
index 91071e9..1caae6b 100644
--- a/board/prodrive/p3mx/p3mx.h
+++ b/board/prodrive/p3mx/p3mx.h
@@ -31,4 +31,3 @@
#define LED_ORANGE 4
#endif /* __P3MX_H__ */
-
diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c
index 859dd7a..1e3dffb 100644
--- a/board/sandburst/common/ppc440gx_i2c.c
+++ b/board/sandburst/common/ppc440gx_i2c.c
@@ -27,13 +27,8 @@
*/
#include <common.h>
#include <ppc4xx.h>
-#if defined(CONFIG_440)
-# include <440_i2c.h>
-#else
-# include <405gp_i2c.h>
-#endif
+#include <4xx_i2c.h>
#include <i2c.h>
-#include <440_i2c.h>
#include <command.h>
#include "ppc440gx_i2c.h"
diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h
index cd4fc86..10000f5 100644
--- a/board/sandburst/common/ppc440gx_i2c.h
+++ b/board/sandburst/common/ppc440gx_i2c.h
@@ -27,11 +27,7 @@
*/
#include <common.h>
#include <ppc4xx.h>
-#if defined(CONFIG_440)
-# include <440_i2c.h>
-#else
-# include <405gp_i2c.h>
-#endif
+#include <4xx_i2c.h>
#include <i2c.h>
#ifdef CONFIG_HARD_I2C
diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c
index d2c8d44..f4074ae 100644
--- a/board/trab/auto_update.c
+++ b/board/trab/auto_update.c
@@ -203,7 +203,6 @@ extern int flash_write (char *, ulong, ulong);
/* change char* to void* to shutup the compiler */
extern int i2c_write_multiple (uchar, uint, int, void *, int);
extern int i2c_read_multiple (uchar, uint, int, void *, int);
-extern block_dev_desc_t *get_dev (char*, int);
extern int u_boot_hush_start(void);
int
diff --git a/board/xilinx/ml300/Makefile b/board/xilinx/ml300/Makefile
index 02c22fb..05ad235 100644
--- a/board/xilinx/ml300/Makefile
+++ b/board/xilinx/ml300/Makefile
@@ -28,7 +28,7 @@ $(shell mkdir -p $(obj)../xilinx_enet)
$(shell mkdir -p $(obj)../xilinx_iic)
endif
-INCS := -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic
+INCS := -I../common -I../xilinx_enet -I../xilinx_iic
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c
index dad562f..60f0bc2 100644
--- a/board/xilinx/ml300/ml300.c
+++ b/board/xilinx/ml300/ml300.c
@@ -38,9 +38,9 @@
*
*/
+#include <config.h>
#include <common.h>
#include <asm/processor.h>
-#include "xparameters.h"
#ifdef CFG_ENV_IS_IN_EEPROM
extern void convert_env(void);
diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c
index c204b88..9b03f89 100644
--- a/board/xilinx/ml300/serial.c
+++ b/board/xilinx/ml300/serial.c
@@ -40,8 +40,7 @@
#include <asm/processor.h>
#include <common.h>
#include <command.h>
-#include <configs/ml300.h>
-#include "xparameters.h"
+#include <config.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c
index b30e897..f159cb6 100644
--- a/board/xilinx/xilinx_enet/emac_adapter.c
+++ b/board/xilinx/xilinx_enet/emac_adapter.c
@@ -37,9 +37,9 @@
*
******************************************************************************/
+#include <config.h>
#include <common.h>
#include <net.h>
-#include "xparameters.h"
#include "xemac.h"
#if defined(XPAR_EMAC_0_DEVICE_ID)
diff --git a/board/xilinx/xilinx_enet/xemac.h b/board/xilinx/xilinx_enet/xemac.h
index ed704bf..584cb7a 100644
--- a/board/xilinx/xilinx_enet/xemac.h
+++ b/board/xilinx/xilinx_enet/xemac.h
@@ -257,9 +257,9 @@
/***************************** Include Files *********************************/
+#include <config.h>
#include "xbasic_types.h"
#include "xstatus.h"
-#include "xparameters.h"
#include "xpacket_fifo_v1_00_b.h" /* Uses v1.00b of Packet Fifo */
#include "xdma_channel.h"
diff --git a/board/xilinx/xilinx_enet/xemac_g.c b/board/xilinx/xilinx_enet/xemac_g.c
index 9340f91..d985157 100644
--- a/board/xilinx/xilinx_enet/xemac_g.c
+++ b/board/xilinx/xilinx_enet/xemac_g.c
@@ -43,7 +43,7 @@
*
*******************************************************************/
-#include "xparameters.h"
+#include <config.h>
#include "xemac.h"
/*
diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c
index 163fe15..37dce03 100644
--- a/board/xilinx/xilinx_iic/iic_adapter.c
+++ b/board/xilinx/xilinx_iic/iic_adapter.c
@@ -37,10 +37,10 @@
*
******************************************************************************/
+#include <config.h>
#include <common.h>
#include <environment.h>
#include <net.h>
-#include "xparameters.h"
#ifdef CFG_ENV_IS_IN_EEPROM
#include <i2c.h>