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| author | Jason Liu <r64343@freescale.com> | 2012-11-16 14:38:40 +0800 |
|---|---|---|
| committer | Xinyu Chen <xinyu.chen@freescale.com> | 2012-11-26 16:45:38 +0800 |
| commit | 8a2873c9bb87b75690c84acf9b73af14c90129ad (patch) | |
| tree | 67b4ad31c01b6101756ba96adfa2811adfae6bb0 /board | |
| parent | e2a77595e560983a2c0ee3efc74b9952dfc1fdeb (diff) | |
| download | u-boot-imx-8a2873c9bb87b75690c84acf9b73af14c90129ad.zip u-boot-imx-8a2873c9bb87b75690c84acf9b73af14c90129ad.tar.gz u-boot-imx-8a2873c9bb87b75690c84acf9b73af14c90129ad.tar.bz2 | |
ENGR00233709-1 i.mx6dl/sabreauto: update the DDR script for i.mx6dl AI board:
This commit update the DDR script for i.MX6DL Sabreauto(AI) board.
The script is based on top the commit on ddr-scripts-rel:
02b8a73 removed some verbage (comments) from init, no changes to actual init
Signed-off-by: Jason Liu <r64343@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6q_sabreauto/flash_header.S | 35 |
1 files changed, 17 insertions, 18 deletions
diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S index 3aa195d..86e2255 100644 --- a/board/freescale/mx6q_sabreauto/flash_header.S +++ b/board/freescale/mx6q_sabreauto/flash_header.S @@ -323,8 +323,8 @@ MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) #elif defined CONFIG_MX6DL_DDR3 -dcd_hdr: .word 0x40B002D2 /* Tag=0xD2, Len=85*8 + 4 + 4, Ver=0x40 */ -write_dcd_cmd: .word 0x04AC02CC /* Tag=0xCC, Len=85*8 + 4, Param=0x04 */ +dcd_hdr: .word 0x40A002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x049C02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */ # IOMUXC_BASE_ADDR = 0x20e0000 # DDR IO TYPE @@ -344,7 +344,7 @@ MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000030) MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000030) MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000030) # Data Strobe -MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00000000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000) MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000028) MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000028) @@ -355,7 +355,7 @@ MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4d0, 0x00000028) MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4d4, 0x00000028) MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d8, 0x00000028) # DATA -MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x760, 0x00000000) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x760, 0x00020000) MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x764, 0x00000028) MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x770, 0x00000028) @@ -420,23 +420,22 @@ MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2) MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x006B1023) MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000047) -MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x400, 0x11420000) -MXC_DCD_ITEM(73, MMDC_P1_BASE_ADDR + 0x400, 0x11420000) -MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000) +MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000) # Initialize 2GB DDR3 - Micron MT41J128M -MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032) -MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033) -MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031) -MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x05208030) -MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) # final DDR setup -MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) -MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) -MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) -MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x004, 0x00025565) -MXC_DCD_ITEM(84, MMDC_P1_BASE_ADDR + 0x404, 0x00011006) -MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) + +MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032) +MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031) +MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x05208030) +MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) +MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) +MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) +MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) +MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x00025565) +MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x404, 0x00011006) +MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) #else |