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| author | Peter Tyser <ptyser@xes-inc.com> | 2009-07-17 19:01:07 -0500 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-07-24 06:42:32 +0200 |
| commit | e02990764c7415c84668823a0fc8c5b4dd8d8cf0 (patch) | |
| tree | 0fd9c7a3346533878759e5a27d49e06dc22b4906 /board/xpedite1k/init.S | |
| parent | 086ff34a3a7e5e595630d658c1c13778399452d1 (diff) | |
| download | u-boot-imx-e02990764c7415c84668823a0fc8c5b4dd8d8cf0.zip u-boot-imx-e02990764c7415c84668823a0fc8c5b4dd8d8cf0.tar.gz u-boot-imx-e02990764c7415c84668823a0fc8c5b4dd8d8cf0.tar.bz2 | |
xpedite1k: Cleanup coding style
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/xpedite1k/init.S')
| -rw-r--r-- | board/xpedite1k/init.S | 67 |
1 files changed, 32 insertions, 35 deletions
diff --git a/board/xpedite1k/init.S b/board/xpedite1k/init.S index 8a04f4f..54371e2 100644 --- a/board/xpedite1k/init.S +++ b/board/xpedite1k/init.S @@ -1,5 +1,5 @@ /* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> +* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> * * See file CREDITS for list of people who contributed to this * project. @@ -24,62 +24,59 @@ #include <config.h> /* General */ -#define TLB_VALID 0x00000200 +#define TLB_VALID 0x00000200 /* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 /* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ /* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ /* Some handy macros */ - #define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) +#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID )) +#define TLB1(rpn,erpn) (((rpn)&0xfffffc00) | (erpn)) +#define TLB2(a) ((a)&0x00000fbf) -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; +#define tlbtab_start \ + mflr r1; \ + bl 0f; -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; +#define tlbtab_end \ + .long 0, 0, 0; \ +0: mflr r0; \ + mtlr r1; \ + blr; #define tlbentry(epn,sz,rpn,erpn,attr)\ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) -/************************************************************************** +/* * TLB TABLE * * This table is used by the cpu boot code to setup the initial tlb * entries. Rather than make broad assumptions in the cpu source tree, * this table lets each board set things up however they like. * - * Pointer to the table is returned in r1 - * - *************************************************************************/ + * Pointer to the table is returned in r1 + */ .section .bootpg,"ax" .globl tlbtab |