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authorYork Sun <yorksun@freescale.com>2008-05-15 15:26:27 -0500
committerWolfgang Denk <wd@denx.de>2008-05-19 23:04:24 +0200
commit4ce1e23b5e12283579828b3d23e8fd6e1328a7aa (patch)
tree4b05bf37a8b0993bdc0d4b2b87bd6b652978179e /board/xilinx
parent180a90abdae72587c0f679edf8991455e559440d (diff)
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Fix 8313ERDB board configuration
Change LCRR clock ratio from 2 to 4 to commodate VSC7385. Correct TSEC1 vs TSEC2 assignment. Define ETHADDR and ETH1ADDR always. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com>
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