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authorNovasys Ingenierie <xilinx@novasys-ingenierie.com>2013-11-27 09:03:01 +0100
committerMichal Simek <michal.simek@xilinx.com>2014-02-06 10:08:03 +0100
commitc83a35f65250a8bdb519cb26680437e5c93d133d (patch)
tree16897cb24add276f1939a6de6283bc11e4de8a0e /board/xilinx/zynq
parente141652b9cd0cb4f899f7a0fd71c8a438300e365 (diff)
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fpga: zynq: Correct fpga load when buf is not aligned
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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