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| author | Michal Simek <monstr@monstr.eu> | 2007-08-05 15:54:53 +0200 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2007-08-05 15:54:53 +0200 |
| commit | 98889edd50aadf862071eb5664747ad0d568a20e (patch) | |
| tree | 7eae4e26a457d35db84f26b9f0dd4da4843611ca /board/xilinx/xupv2p/xparameters.h | |
| parent | 537091b4eed9302865d03fef3f7212b4fe5cf28f (diff) | |
| download | u-boot-imx-98889edd50aadf862071eb5664747ad0d568a20e.zip u-boot-imx-98889edd50aadf862071eb5664747ad0d568a20e.tar.gz u-boot-imx-98889edd50aadf862071eb5664747ad0d568a20e.tar.bz2 | |
[FIX] Change configuration for XUPV2P Microblaze board
Diffstat (limited to 'board/xilinx/xupv2p/xparameters.h')
| -rw-r--r-- | board/xilinx/xupv2p/xparameters.h | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/board/xilinx/xupv2p/xparameters.h b/board/xilinx/xupv2p/xparameters.h index a96c693..0bb7a80 100644 --- a/board/xilinx/xupv2p/xparameters.h +++ b/board/xilinx/xupv2p/xparameters.h @@ -28,17 +28,24 @@ /* System Clock Frequency */ #define XILINX_CLOCK_FREQ 100000000 +/* Microblaze is microblaze_0 */ +#define XILINX_USE_MSR_INSTR 1 +#define XILINX_PVR 0 +#define XILINX_FSL_NUMBER 0 + /* Interrupt controller is opb_intc_0 */ #define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 11 +#define XILINX_INTC_NUM_INTR_INPUTS 7 /* Timer pheriphery is opb_timer_1 */ #define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 1 +#define XILINX_TIMER_IRQ 0 /* Uart pheriphery is RS232_Uart_1 */ -#define XILINX_UART_BASEADDR 0x40600000 -#define XILINX_UART_BAUDRATE 115200 +#define XILINX_UARTLITE_BASEADDR 0x40600000 +#define XILINX_UARTLITE_BAUDRATE 115200 + +/* IIC doesn't exist */ /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 @@ -51,14 +58,10 @@ /* Sysace Controller is SysACE_CompactFlash */ #define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff #define XILINX_SYSACE_MEM_WIDTH 16 /* Ethernet controller is Ethernet_MAC */ -#define XPAR_XEMAC_NUM_INSTANCES 1 -#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 -#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff -#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 -#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 -#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 +#define XILINX_EMAC_BASEADDR 0x40c00000 +#define XILINX_EMAC_DMA_PRESENT 3 +#define XILINX_EMAC_HALF_DUPLEX_EXIST 1 +#define XILINX_EMAC_MII_EXIST 1 |