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| author | Michal Simek <root@monstr.eu> | 2007-03-26 01:39:07 +0200 |
|---|---|---|
| committer | Michal Simek <root@monstr.eu> | 2007-03-26 01:39:07 +0200 |
| commit | 1798049522f594013aea29457d46794298c6ae15 (patch) | |
| tree | 966edd78aadda268b6412e616c051602f99a6094 /board/xilinx/xupv2p/xparameters.h | |
| parent | cfc67116a706fd18b8f6a9c11a16753c5626d689 (diff) | |
| download | u-boot-imx-1798049522f594013aea29457d46794298c6ae15.zip u-boot-imx-1798049522f594013aea29457d46794298c6ae15.tar.gz u-boot-imx-1798049522f594013aea29457d46794298c6ae15.tar.bz2 | |
Support for XUPV2P board
Reset support
BSP autoconfig support
Diffstat (limited to 'board/xilinx/xupv2p/xparameters.h')
| -rw-r--r-- | board/xilinx/xupv2p/xparameters.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/board/xilinx/xupv2p/xparameters.h b/board/xilinx/xupv2p/xparameters.h new file mode 100644 index 0000000..fc7d6e7 --- /dev/null +++ b/board/xilinx/xupv2p/xparameters.h @@ -0,0 +1,46 @@ +/********************************************************************* +# +# CAUTION: This file is automatically generated by libgen. +# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 +# Description: U-BOOT Configuration File +# Michal Simek - monstr@monstr.eu +# +**********************************************************************/ + +/* System Clock Frequency */ +#define XILINX_CLOCK_FREQ 100000000 + +/* Interrupt controller is opb_intc_0 */ +#define XILINX_INTC_BASEADDR 0x41200000 +#define XILINX_INTC_NUM_INTR_INPUTS 11 + +/* Timer pheriphery is opb_timer_1 */ +#define XILINX_TIMER_BASEADDR 0x41c00000 +#define XILINX_TIMER_IRQ 1 + +/* Uart pheriphery is RS232_Uart_1 */ +#define XILINX_UART_BASEADDR 0x40600000 +#define XILINX_UART_BAUDRATE 115200 + +/* GPIO is LEDs_4Bit*/ +#define XILINX_GPIO_BASEADDR 0x40000000 + +/* FLASH doesn't exist none */ + +/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */ +#define XILINX_RAM_START 0x30000000 +#define XILINX_RAM_SIZE 0x10000000 + +/* Sysace Controller is SysACE_CompactFlash */ +#define XILINX_SYSACE_BASEADDR 0x41800000 +#define XILINX_SYSACE_HIGHADDR 0x4180ffff +#define XILINX_SYSACE_MEM_WIDTH 16 + +/* Ethernet controller is Ethernet_MAC */ +#define XPAR_XEMAC_NUM_INSTANCES 1 +#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 +#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 |