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| author | Peter Tyser <ptyser@xes-inc.com> | 2009-10-23 15:55:48 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-10-27 09:34:58 -0500 |
| commit | 48618126f78f05042dae428811809b594f747eb9 (patch) | |
| tree | 6521b730c69328a7d90da5c1d7e4b19cb66f1345 /board/xes/xpedite5370/tlb.c | |
| parent | 5ccd29c3679b3669b0bde5c501c1aa0f325a7acb (diff) | |
| download | u-boot-imx-48618126f78f05042dae428811809b594f747eb9.zip u-boot-imx-48618126f78f05042dae428811809b594f747eb9.tar.gz u-boot-imx-48618126f78f05042dae428811809b594f747eb9.tar.bz2 | |
xpedite5370: Enable multi-core support
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/xes/xpedite5370/tlb.c')
| -rw-r--r-- | board/xes/xpedite5370/tlb.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite5370/tlb.c index caafa30..a465ce3 100644 --- a/board/xes/xpedite5370/tlb.c +++ b/board/xes/xpedite5370/tlb.c @@ -61,32 +61,37 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), + /* **M** - Boot page for secondary processors */ + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 3, BOOKE_PAGESZ_4K, 1), + #ifdef CONFIG_PCIE1 /* *I*G* - PCIe */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), + 0, 4, BOOKE_PAGESZ_1G, 1), #endif #ifdef CONFIG_PCIE2 /* *I*G* - PCIe */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), + 0, 5, BOOKE_PAGESZ_256M, 1), #endif #ifdef CONFIG_PCIE3 /* *I*G* - PCIe */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), + 0, 6, BOOKE_PAGESZ_256M, 1), #endif #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) /* *I*G* - PCIe */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), + 0, 7, BOOKE_PAGESZ_64M, 1), #endif }; |