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authorKumar Gala <galak@kernel.crashing.org>2011-01-31 22:18:47 -0600
committerKumar Gala <galak@kernel.crashing.org>2011-04-04 09:24:41 -0500
commitc39f44dc6f5ae843d5def511f6e71d4b012dc598 (patch)
treed863c3a3e87967d01e4de1021bd20abe3b57af7a /board/xes/xpedite517x
parent5df4b0ad0dff3cef1bd6660bcc8cba028c80adcb (diff)
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powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/xes/xpedite517x')
-rw-r--r--board/xes/xpedite517x/ddr.c25
1 files changed, 1 insertions, 24 deletions
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
index 981bf41..3a6e297 100644
--- a/board/xes/xpedite517x/ddr.c
+++ b/board/xes/xpedite517x/ddr.c
@@ -26,35 +26,12 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
sizeof(ddr2_spd_eeprom_t));
}
-void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
-{
- unsigned int i;
- unsigned int i2c_address = 0;
-
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (ctrl_num == 0) {
- i2c_address = SPD_EEPROM_ADDRESS1;
-#ifdef SPD_EEPROM_ADDRESS2
- } else if (ctrl_num == 1) {
- i2c_address = SPD_EEPROM_ADDRESS2;
-#endif
- } else {
- /* An inalid ctrl number was give, use default SPD */
- printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num);
- i2c_address = SPD_EEPROM_ADDRESS1;
- }
-
- get_spd(&(ctrl_dimms_spd[i]), i2c_address);
- }
-}
-
/*
* There are four board-specific SDRAM timing parameters which must be
* calculated based on the particular PCB artwork. These are: