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authorBecky Bruce <beckyb@kernel.crashing.org>2010-12-17 17:17:56 -0600
committerKumar Gala <galak@kernel.crashing.org>2011-01-14 01:32:19 -0600
commit38dba0c2ff685e3f8276a236bd70eaa09c84ead5 (patch)
treefc3365f6bdd25dfe23f2ec8c02926907613c8520 /board/xes/common/Makefile
parent6b1ef2a6a553c33e74c5e50c77b55d40af669be3 (diff)
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mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/xes/common/Makefile')
-rw-r--r--board/xes/common/Makefile2
1 files changed, 0 insertions, 2 deletions
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index 7604f62..39d105f 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o
-COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
-COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o
COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o