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| author | Pardeep Kumar Singla <b45784@freescale.com> | 2013-07-25 12:12:13 -0500 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-07-27 10:49:36 +0200 |
| commit | 5ea7f0e328c19542ce96d8242125b51b3dbca86b (patch) | |
| tree | 1f80f394227a73e7760c48cf3cfefb5516cb1eba /board/wandboard | |
| parent | f8b1e86d4707718e52cf6466845e463c358627ee (diff) | |
| download | u-boot-imx-5ea7f0e328c19542ce96d8242125b51b3dbca86b.zip u-boot-imx-5ea7f0e328c19542ce96d8242125b51b3dbca86b.tar.gz u-boot-imx-5ea7f0e328c19542ce96d8242125b51b3dbca86b.tar.bz2 | |
mx6: Factor out common HDMI setup code
Instead of duplicating HDMI setup code for every mx6 board, factor out the common code
Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
Diffstat (limited to 'board/wandboard')
| -rw-r--r-- | board/wandboard/wandboard.c | 44 |
1 files changed, 4 insertions, 40 deletions
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 43c02ac..6cd28ed 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -211,23 +211,6 @@ int board_phy_config(struct phy_device *phydev) } #if defined(CONFIG_VIDEO_IPUV3) -static void enable_hdmi(void) -{ - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg; - reg = readb(&hdmi->phy_conf0); - reg |= HDMI_PHY_CONF0_PDZ_MASK; - writeb(reg, &hdmi->phy_conf0); - - udelay(3000); - reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - writeb(reg, &hdmi->phy_conf0); - udelay(3000); - reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - writeb(reg, &hdmi->phy_conf0); - writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); -} - static struct fb_videomode const hdmi = { .name = "HDMI", .refresh = 60, @@ -253,7 +236,7 @@ int board_video_skip(void) if (ret) printf("HDMI cannot be configured: %d\n", ret); - enable_hdmi(); + imx_enable_hdmi_phy(); return ret; } @@ -261,33 +244,14 @@ int board_video_skip(void) static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; int reg; - /* Turn on IPU clock */ - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; - writel(reg, &mxc_ccm->CCGR3); - - /* Turn on HDMI PHY clock */ - reg = readl(&mxc_ccm->CCGR2); - reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK - | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; - writel(reg, &mxc_ccm->CCGR2); - - /* clear HDMI PHY reset */ - writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + enable_ipu_clock(); + imx_setup_hdmi(); reg = readl(&mxc_ccm->chsccdr); - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK - | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK - | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) - | (CHSCCDR_PODF_DIVIDE_BY_3 - << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) - | (CHSCCDR_IPU_PRE_CLK_540M_PFD - << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); } #endif /* CONFIG_VIDEO_IPUV3 */ |