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author | Andy Fleming <afleming@gmail.com> | 2015-11-04 15:48:32 -0600 |
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committer | York Sun <yorksun@freescale.com> | 2015-11-04 15:19:34 -0800 |
commit | 87e29878caba758ed3e09e9912ac8eb6dfc55f39 (patch) | |
tree | d98b04c33498eb2bb30dac21961d1bb32637823c /board/varisys/cyrus/pbi.cfg | |
parent | c79e1c1ce9e5c1ddf6fac631e4741999f8a0cc58 (diff) | |
download | u-boot-imx-87e29878caba758ed3e09e9912ac8eb6dfc55f39.zip u-boot-imx-87e29878caba758ed3e09e9912ac8eb6dfc55f39.tar.gz u-boot-imx-87e29878caba758ed3e09e9912ac8eb6dfc55f39.tar.bz2 |
mpc85xx: Add support for the Varisys Cyrus board
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox <adrian at humboldt dot co dot uk>
Signed-off-by: Andy Fleming <afleming@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/varisys/cyrus/pbi.cfg')
-rw-r--r-- | board/varisys/cyrus/pbi.cfg | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/board/varisys/cyrus/pbi.cfg b/board/varisys/cyrus/pbi.cfg new file mode 100644 index 0000000..9b330dd --- /dev/null +++ b/board/varisys/cyrus/pbi.cfg @@ -0,0 +1,35 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#PBI commands +#Initialize CPC1 as 1MB SRAM +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 |