* Patch by Marc Singer, 29 May 2003:

  Fixed rarp boot method for IA32 and other little-endian CPUs.

* Patch by Marc Singer, 28 May 2003:
  Added port I/O commands.

* Patch by Matthew McClintock, 28 May 2003
  - cpu/mpc824x/start.S: fix relocation code when booting from RAM
  - minor patches for utx8245

* Patch by Daniel Engström, 28 May 2003:
  x86 update

* Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
  add nand flash support to SXNI855T configuration
  fix/extend nand flash support:
  - fix 'nand erase' command so does not erase bad blocks
  - fix 'nand write' command so does not write to bad blocks
  - fix nand_probe() so handles no flash detected properly
  - add doc/README.nand
  - add .jffs2 and .oob options to nand read/write
  - add 'nand bad' command to list bad blocks
  - add 'clean' option to 'nand erase' to write JFFS2 clean markers
  - make NAND read/write faster

* Patch by Rune Torgersen, 23 May 2003:
  Update for MPC8266ADS board

1 files changed, 25 insertions, 12 deletions

diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c
index 63b4e3e..a8c82e4 100644
--- a/board/utx8245/utx8245.c
+++ b/board/utx8245/utx8245.c
@@ -30,6 +30,7 @@
 #include <mpc824x.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
 #include <pci.h>
 
 #define	SAVE_SZ	32
@@ -53,11 +54,18 @@ long int initdram(int board_type)
 	volatile ulong	*addr;
 	ulong			save[SAVE_SZ];
 	ulong			val, ret  = 0;
+/*
+	write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
+			( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
+
+	write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
+			( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
+*/
+	for (i=0; i<SAVE_SZ; i++) {
+		save[i] = 0;		/* clear table */
+	}
 
-	for (i=0; i<SAVE_SZ; i++)	{save[i] = 0;}		/* clear table */
-
-	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1)
-	{
+	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
 		addr = (volatile ulong *)base + cnt;
 		save[i++] = *addr;
 		*addr = ~cnt;
@@ -67,19 +75,16 @@ long int initdram(int board_type)
 	save[i] = *addr;
 	*addr = 0;
 
-	if (*addr != 0)
-	{
+	if (*addr != 0) {
 		*addr = save[i];
 		goto Done;
 	}
 
-	for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1)
-	{
+	for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
 		addr = (volatile ulong *)base + cnt;
 		val = *addr;
 		*addr = save[--i];
-		if (val != ~cnt)
-		{
+		if (val != ~cnt) {
 			ulong new_bank0_end = cnt * sizeof(long) - 1;
 			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
 			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
@@ -111,11 +116,11 @@ Done:
 
 static struct pci_config_table pci_utx8245_config_table[] = {
 #ifndef CONFIG_PCI_PNP
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID,
 	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 				       PCI_ENET0_MEMADDR,
 				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID,
 	  pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
 				       PCI_FIREWIRE_MEMADDR,
 				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
@@ -133,6 +138,14 @@ static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 	else if (PCI_DEV(dev) == 12)
 		/* assign serial interrupt line 8 (int24) to Ethernet */
 		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
+
+	else if (PCI_DEV(dev) == 14)
+		/* assign serial interrupt line 0 (int16) to PMC slot 0 */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16);
+
+	else if (PCI_DEV(dev) == 15)
+		/* assign serial interrupt line 1 (int17) to PMC slot 1 */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17);
 }
 
 static struct pci_controller utx8245_hose = {