Add generic support for samsung s3c2440

This patch adds generic support for the Samsung s3c2440 processor.

Global s3c24x0 changes to struct members converting from upper case to
lower case.

Signed-off-by: Craig Nauman <cnauman@diagraph.com>
Cc: kevin.morfitt@fearnside-systems.co.uk
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

7 files changed, 252 insertions, 240 deletions

diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
index ca4415c..dec3c61 100644
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
@@ -637,28 +637,28 @@ static int adc_read (unsigned int channel)
 
 	adc_init ();
 
-	padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
-	padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
-	padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+	padc->adccon &= ~ADC_STDBM; /* select normal mode */
+	padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+	padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
 
 	while (j--) {
-		if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+		if ((padc->adccon & ADC_ENABLE_START) == 0)
 			break;
 		udelay (1);
 	}
 
 	if (j == 0) {
 		printf("%s: ADC timeout\n", __FUNCTION__);
-		padc->ADCCON |= ADC_STDBM; /* select standby mode */
+		padc->adccon |= ADC_STDBM; /* select standby mode */
 		return -1;
 	}
 
-	result = padc->ADCDAT & 0x3FF;
+	result = padc->adcdat & 0x3FF;
 
-	padc->ADCCON |= ADC_STDBM; /* select standby mode */
+	padc->adccon |= ADC_STDBM; /* select standby mode */
 
 	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
-	       (padc->ADCCON >> 3) & 0x7, result);
+	       (padc->adccon >> 3) & 0x7, result);
 
 	/*
 	 * Wait for ADC to be ready for next conversion. This delay value was
@@ -676,8 +676,8 @@ static void adc_init (void)
 
 	padc = s3c2400_get_base_adc();
 
-	padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
-	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+	padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+	padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
 
 	/*
 	 * Wait some time to avoid problem with very first call of
@@ -699,10 +699,10 @@ static void led_set (unsigned int state)
 
 	switch (state) {
 	case 0: /* turn LED off */
-		gpio->PADAT |= (1 << 12);
+		gpio->padat |= (1 << 12);
 		break;
 	case 1: /* turn LED on */
-		gpio->PADAT &= ~(1 << 12);
+		gpio->padat &= ~(1 << 12);
 		break;
 	default:
 		break;
@@ -729,8 +729,8 @@ static void led_init (void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure GPA12 as output and set to High -> LED off */
-	gpio->PACON &= ~(1 << 12);
-	gpio->PADAT |= (1 << 12);
+	gpio->pacon &= ~(1 << 12);
+	gpio->padat |= (1 << 12);
 }
 
 
diff --git a/board/trab/rs485.c b/board/trab/rs485.c
index 6a3a4cd..30336f2 100644
--- a/board/trab/rs485.c
+++ b/board/trab/rs485.c
@@ -51,16 +51,16 @@ static void rs485_setbrg (void)
 	reg = (33000000 / (16 * 38400)) - 1;
 
 	/* FIFO enable, Tx/Rx FIFO clear */
-	uart->UFCON = 0x07;
-	uart->UMCON = 0x0;
+	uart->ufcon = 0x07;
+	uart->umcon = 0x0;
 	/* Normal,No parity,1 stop,8 bit */
-	uart->ULCON = 0x3;
+	uart->ulcon = 0x3;
 	/*
 	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal,interrupt or polling
 	 */
-	uart->UCON = 0x245;
-	uart->UBRDIV = reg;
+	uart->ucon = 0x245;
+	uart->ubrdiv = reg;
 
 	for (i = 0; i < 100; i++);
 }
@@ -69,16 +69,16 @@ static void rs485_cfgio (void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PFCON &= ~(0x3 << 2);
-	gpio->PFCON |=  (0x2 << 2); /* configure GPF1 as RXD1 */
+	gpio->pfcon &= ~(0x3 << 2);
+	gpio->pfcon |=  (0x2 << 2); /* configure GPF1 as RXD1 */
 
-	gpio->PFCON &= ~(0x3 << 6);
-	gpio->PFCON |=  (0x2 << 6); /* configure GPF3 as TXD1 */
+	gpio->pfcon &= ~(0x3 << 6);
+	gpio->pfcon |=  (0x2 << 6); /* configure GPF3 as TXD1 */
 
-	gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
-	gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
+	gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */
+	gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */
 
-	gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+	gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
 }
 
 /*
@@ -104,9 +104,10 @@ int rs485_getc (void)
 	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
 	/* wait for character to arrive */
-	while (!(uart->UTRSTAT & 0x1));
+	while (!(uart->utrstat & 0x1))
+		;
 
-	return uart->URXH & 0xff;
+	return uart->urxh & 0xff;
 }
 
 /*
@@ -117,9 +118,10 @@ void rs485_putc (const char c)
 	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
 	/* wait for room in the tx FIFO */
-	while (!(uart->UTRSTAT & 0x2));
+	while (!(uart->utrstat & 0x2))
+		;
 
-	uart->UTXH = c;
+	uart->utxh = c;
 
 	/* If \n, also do \r */
 	if (c == '\n')
@@ -133,7 +135,7 @@ int rs485_tstc (void)
 {
 	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
-	return uart->UTRSTAT & 0x1;
+	return uart->utrstat & 0x1;
 }
 
 void rs485_puts (const char *s)
@@ -172,9 +174,9 @@ static void set_rs485de(unsigned char rs485de_state)
 
 	/* This is on PORT A bit 11 */
 	if(rs485de_state)
-		gpio->PADAT |= (1 << 11);
+		gpio->padat |= (1 << 11);
 	else
-		gpio->PADAT &= ~(1 << 11);
+		gpio->padat &= ~(1 << 11);
 }
 
 
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 828facd..0f74e8f 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -77,36 +77,36 @@ int board_init ()
 #ifdef CONFIG_TRAB_50MHZ
 	/* change the clock to be 50 MHz 1:1:1 */
 	/* MDIV:0x5c PDIV:4 SDIV:2 */
-	clk_power->MPLLCON = 0x5c042;
-	clk_power->CLKDIVN = 0;
+	clk_power->mpllcon = 0x5c042;
+	clk_power->clkdivn = 0;
 #else
 	/* change the clock to be 133 MHz 1:2:4 */
 	/* MDIV:0x7d PDIV:4 SDIV:1 */
-	clk_power->MPLLCON = 0x7d041;
-	clk_power->CLKDIVN = 3;
+	clk_power->mpllcon = 0x7d041;
+	clk_power->clkdivn = 3;
 #endif
 
 	/* set up the I/O ports */
-	gpio->PACON = 0x3ffff;
-	gpio->PBCON = 0xaaaaaaaa;
-	gpio->PBUP  = 0xffff;
+	gpio->pacon = 0x3ffff;
+	gpio->pbcon = 0xaaaaaaaa;
+	gpio->pbup  = 0xffff;
 	/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0]	*/
 	/*  00,    10,      10,      10,      10,      10,      10	*/
-	gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+	gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
 #ifdef CONFIG_HWFLOW
 	/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
-	gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+	gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
 #else
 	/* do not pull up RXD0, RXD1, TXD0, TXD1 */
-	gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+	gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
 #endif
-	gpio->PGCON = 0x0;
-	gpio->PGUP  = 0x0;
-	gpio->OPENCR= 0x0;
+	gpio->pgcon = 0x0;
+	gpio->pgup  = 0x0;
+	gpio->opencr = 0x0;
 
 	/* suppress flicker of the VFDs */
-	gpio->MISCCR = 0x40;
-	gpio->PFCON |= (2<<12);
+	gpio->misccr = 0x40;
+	gpio->pfcon |= (2<<12);
 
 	gd->bd->bi_arch_number = MACH_TYPE_TRAB;
 
@@ -114,8 +114,8 @@ int board_init ()
 	gd->bd->bi_boot_params = 0x0c000100;
 
 	/* Make sure both buzzers are turned off */
-	gpio->PDCON |= 0x5400;
-	gpio->PDDAT &= ~0xE0;
+	gpio->pdcon |= 0x5400;
+	gpio->pddat &= ~0xE0;
 
 #ifdef CONFIG_VFD
 	vfd_init_clocks();
@@ -132,7 +132,7 @@ int board_init ()
 
 #ifdef CONFIG_DRIVER_S3C24X0_I2C
 	/* Configure I/O ports PG5 und PG6 for I2C */
-	gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+	gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00;
 #endif /* CONFIG_DRIVER_S3C24X0_I2C */
 
 	return 0;
@@ -341,14 +341,14 @@ static inline void SET_CS_TOUCH(void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PDDAT &= 0x5FF;
+	gpio->pddat &= 0x5FF;
 }
 
 static inline void CLR_CS_TOUCH(void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PDDAT |= 0x200;
+	gpio->pddat |= 0x200;
 }
 
 static void spi_init(void)
@@ -358,20 +358,20 @@ static void spi_init(void)
 	int i;
 
 	/* Configure I/O ports. */
-	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
-	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
-	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
-	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+	gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+	gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+	gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+	gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
 
 	CLR_CS_TOUCH();
 
-	spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
-	spi->ch[0].SPPIN = 0x01;  /* SPI-MOSI holds Level after last bit */
-	spi->ch[0].SPCON = 0x1A;  /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
+	spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */
+	spi->ch[0].sppin = 0x01;  /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].spcon = 0x1A; /* Polling, Prescale, Master, CPOL=0, CPHA=1 */
 
 	/* Dummy byte ensures clock to be low. */
 	for (i = 0; i < 10; i++) {
-		spi->ch[0].SPTDAT = 0xFF;
+		spi->ch[0].sptdat = 0xFF;
 	}
 	wait_transmit_done();
 }
@@ -380,7 +380,8 @@ static void wait_transmit_done(void)
 {
 	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
 
-	while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+	while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+		;
 }
 
 static void tsc2000_write(unsigned int page, unsigned int reg,
@@ -394,13 +395,13 @@ static void tsc2000_write(unsigned int page, unsigned int reg,
 	command |= (page << 11);
 	command |= (reg << 5);
 
-	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
 	wait_transmit_done();
-	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi->ch[0].sptdat = (command & 0x00FF);
 	wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (data & 0xFF00) >> 8;
 	wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0x00FF);
+	spi->ch[0].sptdat = (data & 0x00FF);
 	wait_transmit_done();
 
 	CLR_CS_TOUCH();
diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c
index 268162e..fe3dab3 100644
--- a/board/trab/trab_fkt.c
+++ b/board/trab/trab_fkt.c
@@ -411,28 +411,28 @@ static int adc_read (unsigned int channel)
 	padc = s3c2400_get_base_adc();
 	channel &= 0x7;
 
-	padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
-	padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
-	padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+	padc->adccon &= ~ADC_STDBM; /* select normal mode */
+	padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+	padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
 
 	while (j--) {
-		if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+		if ((padc->adccon & ADC_ENABLE_START) == 0)
 			break;
 		udelay (1);
 	}
 
 	if (j == 0) {
 		printf("%s: ADC timeout\n", __FUNCTION__);
-		padc->ADCCON |= ADC_STDBM; /* select standby mode */
+		padc->adccon |= ADC_STDBM; /* select standby mode */
 		return -1;
 	}
 
-	result = padc->ADCDAT & 0x3FF;
+	result = padc->adcdat & 0x3FF;
 
-	padc->ADCCON |= ADC_STDBM; /* select standby mode */
+	padc->adccon |= ADC_STDBM; /* select standby mode */
 
 	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
-	       (padc->ADCCON >> 3) & 0x7, result);
+	       (padc->adccon >> 3) & 0x7, result);
 
 	/*
 	 * Wait for ADC to be ready for next conversion. This delay value was
@@ -450,8 +450,8 @@ static void adc_init (void)
 
 	padc = s3c2400_get_base_adc();
 
-	padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
-	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+	padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+	padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
 
 	/*
 	 * Wait some time to avoid problem with very first call of
@@ -493,10 +493,10 @@ int do_power_switch (void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure GPE7 as input */
-	gpio->PECON &= ~(0x3 << (2 * 7));
+	gpio->pecon &= ~(0x3 << (2 * 7));
 
 	/* signal GPE7 from power switch is low active: 0=on , 1=off */
-	result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1;
+	result = ((gpio->pedat & (1 << 7)) == (1 << 7)) ? 0 : 1;
 
 	print_identifier ();
 	printf("%d\n", result);
@@ -561,17 +561,17 @@ int do_vfd_id (void)
 
 	/* try to red vfd board id from the value defined by pull-ups */
 
-	pcup_old = gpio->PCUP;
-	pccon_old = gpio->PCCON;
+	pcup_old = gpio->pcup;
+	pccon_old = gpio->pccon;
 
-	gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate  GPC0...GPC3 pull-ups */
-	gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as
+	gpio->pcup = (gpio->pcup & 0xFFF0); /* activate  GPC0...GPC3 pull-ups */
+	gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* configure GPC0...GPC3 as
 						   * inputs */
 	udelay (10);            /* allow signals to settle */
-	vfd_board_id = (~gpio->PCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
+	vfd_board_id = (~gpio->pcdat) & 0x000F;	/* read GPC0...GPC3 port pins */
 
-	gpio->PCCON = pccon_old;
-	gpio->PCUP = pcup_old;
+	gpio->pccon = pccon_old;
+	gpio->pcup = pcup_old;
 
 	/* print vfd_board_id to console */
 	print_identifier ();
@@ -593,40 +593,40 @@ int do_buzzer (char * const *argv)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* set prescaler for timer 2, 3 and 4 */
-	timers->TCFG0 &= ~0xFF00;
-	timers->TCFG0 |=  0x0F00;
+	timers->tcfg0 &= ~0xFF00;
+	timers->tcfg0 |=  0x0F00;
 
 	/* set divider for timer 2 */
-	timers->TCFG1 &= ~0xF00;
-	timers->TCFG1 |=  0x300;
+	timers->tcfg1 &= ~0xF00;
+	timers->tcfg1 |=  0x300;
 
 	/* set frequency */
 	counter = (PCLK / BUZZER_FREQ) >> 9;
-	timers->ch[2].TCNTB = counter;
-	timers->ch[2].TCMPB = counter / 2;
+	timers->ch[2].tcntb = counter;
+	timers->ch[2].tcmpb = counter / 2;
 
 	if (strcmp (argv[2], "on") == 0) {
 		debug ("%s: frequency: %d\n", __FUNCTION__,
 		       BUZZER_FREQ);
 
 		/* configure pin GPD7 as TOUT2 */
-		gpio->PDCON &= ~0xC000;
-		gpio->PDCON |= 0x8000;
+		gpio->pdcon &= ~0xC000;
+		gpio->pdcon |= 0x8000;
 
 		/* start */
-		timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) &
+		timers->tcon = (timers->tcon | UPDATE2 | RELOAD2) &
 				~INVERT2;
-		timers->TCON = (timers->TCON | START2) & ~UPDATE2;
+		timers->tcon = (timers->tcon | START2) & ~UPDATE2;
 		return (0);
 	}
 	else if (strcmp (argv[2], "off") == 0) {
 		/* stop */
-		timers->TCON &= ~(START2 | RELOAD2);
+		timers->tcon &= ~(START2 | RELOAD2);
 
 		/* configure GPD7 as output and set to low */
-		gpio->PDCON &= ~0xC000;
-		gpio->PDCON |= 0x4000;
-		gpio->PDDAT &= ~0x80;
+		gpio->pdcon &= ~0xC000;
+		gpio->pdcon |= 0x4000;
+		gpio->pddat &= ~0x80;
 		return (0);
 	}
 
@@ -640,12 +640,12 @@ int do_led (char * const *argv)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure PC14 and PC15 as output */
-	gpio->PCCON &= ~(0xF << 28);
-	gpio->PCCON |= (0x5 << 28);
+	gpio->pccon &= ~(0xF << 28);
+	gpio->pccon |= (0x5 << 28);
 
 	/* configure PD0 and PD4 as output */
-	gpio->PDCON &= ~((0x3 << 8) | 0x3);
-	gpio->PDCON |= ((0x1 << 8) | 0x1);
+	gpio->pdcon &= ~((0x3 << 8) | 0x3);
+	gpio->pdcon |= ((0x1 << 8) | 0x1);
 
 	switch (simple_strtoul(argv[2], NULL, 10)) {
 
@@ -655,30 +655,30 @@ int do_led (char * const *argv)
 
 	case 2:
 		if (strcmp (argv[3], "on") == 0)
-			gpio->PCDAT |= (1 << 14);
+			gpio->pcdat |= (1 << 14);
 		else
-			gpio->PCDAT &= ~(1 << 14);
+			gpio->pcdat &= ~(1 << 14);
 		return 0;
 
 	case 3:
 		if (strcmp (argv[3], "on") == 0)
-			gpio->PCDAT |= (1 << 15);
+			gpio->pcdat |= (1 << 15);
 		else
-			gpio->PCDAT &= ~(1 << 15);
+			gpio->pcdat &= ~(1 << 15);
 		return 0;
 
 	case 4:
 		if (strcmp (argv[3], "on") == 0)
-			gpio->PDDAT |= (1 << 0);
+			gpio->pddat |= (1 << 0);
 		else
-			gpio->PDDAT &= ~(1 << 0);
+			gpio->pddat &= ~(1 << 0);
 		return 0;
 
 	case 5:
 		if (strcmp (argv[3], "on") == 0)
-			gpio->PDDAT |= (1 << 4);
+			gpio->pddat |= (1 << 4);
 		else
-			gpio->PDDAT &= ~(1 << 4);
+			gpio->pddat &= ~(1 << 4);
 		return 0;
 
 	default:
@@ -695,22 +695,22 @@ int do_full_bridge (char * const *argv)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure PD5 and PD6 as output */
-	gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2));
-	gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2));
+	gpio->pdcon &= ~((0x3 << 5*2) | (0x3 << 6*2));
+	gpio->pdcon |= ((0x1 << 5*2) | (0x1 << 6*2));
 
 	if (strcmp (argv[2], "+") == 0) {
-	      gpio->PDDAT |= (1 << 5);
-	      gpio->PDDAT |= (1 << 6);
+		gpio->pddat |= (1 << 5);
+	      gpio->pddat |= (1 << 6);
 	      return 0;
 	}
 	else if (strcmp (argv[2], "-") == 0) {
-		gpio->PDDAT &= ~(1 << 5);
-		gpio->PDDAT |= (1 << 6);
+		gpio->pddat &= ~(1 << 5);
+		gpio->pddat |= (1 << 6);
 		return 0;
 	}
 	else if (strcmp (argv[2], "off") == 0) {
-		gpio->PDDAT &= ~(1 << 5);
-		gpio->PDDAT &= ~(1 << 6);
+		gpio->pddat &= ~(1 << 5);
+		gpio->pddat &= ~(1 << 6);
 		return 0;
 	}
 	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
@@ -804,15 +804,15 @@ int do_motor (char * const *argv)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* Configure I/O port */
-	gpio->PGCON &= ~(0x3 << 0);
-	gpio->PGCON |= (0x1 << 0);
+	gpio->pgcon &= ~(0x3 << 0);
+	gpio->pgcon |= (0x1 << 0);
 
 	if (strcmp (argv[2], "on") == 0) {
-		gpio->PGDAT &= ~(1 << 0);
+		gpio->pgdat &= ~(1 << 0);
 		return 0;
 	}
 	if (strcmp (argv[2], "off") == 0) {
-		gpio->PGDAT |= (1 << 0);
+		gpio->pgdat |= (1 << 0);
 		return 0;
 	}
 	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
@@ -832,36 +832,36 @@ int do_pwm (char * const *argv)
 
 	if (strcmp (argv[2], "on") == 0) {
 		/* configure pin GPD8 as TOUT3 */
-		gpio->PDCON &= ~(0x3 << 8*2);
-		gpio->PDCON |= (0x2 << 8*2);
+		gpio->pdcon &= ~(0x3 << 8*2);
+		gpio->pdcon |= (0x2 << 8*2);
 
 		/* set prescaler for timer 2, 3 and 4 */
-		timers->TCFG0 &= ~0xFF00;
-		timers->TCFG0 |= 0x0F00;
+		timers->tcfg0 &= ~0xFF00;
+		timers->tcfg0 |= 0x0F00;
 
 		/* set divider for timer 3 */
-		timers->TCFG1 &= ~(0xf << 12);
-		timers->TCFG1 |= (0x3 << 12);
+		timers->tcfg1 &= ~(0xf << 12);
+		timers->tcfg1 |= (0x3 << 12);
 
 		/* set frequency */
 		counter = (PCLK / PWM_FREQ) >> 9;
-		timers->ch[3].TCNTB = counter;
-		timers->ch[3].TCMPB = counter / 2;
+		timers->ch[3].tcntb = counter;
+		timers->ch[3].tcmpb = counter / 2;
 
 		/* start timer */
-		timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
-		timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+		timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->tcon = (timers->tcon | START3) & ~UPDATE3;
 		return 0;
 	}
 	if (strcmp (argv[2], "off") == 0) {
 
 		/* stop timer */
-		timers->TCON &= ~(START2 | RELOAD2);
+		timers->tcon &= ~(START2 | RELOAD2);
 
 		/* configure pin GPD8 as output and set to 0 */
-		gpio->PDCON &= ~(0x3 << 8*2);
-		gpio->PDCON |= (0x1 << 8*2);
-		gpio->PDDAT &= ~(1 << 8);
+		gpio->pdcon &= ~(0x3 << 8*2);
+		gpio->pdcon |= (0x1 << 8*2);
+		gpio->pddat &= ~(1 << 8);
 		return 0;
 	}
 	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c
index 5890624..426ed9c 100644
--- a/board/trab/tsc2000.c
+++ b/board/trab/tsc2000.c
@@ -50,21 +50,21 @@ void tsc2000_spi_init(void)
 	int i;
 
 	/* Configure I/O ports. */
-	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
-	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
-	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
-	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+	gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+	gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+	gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+	gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
 
 	CLR_CS_TOUCH();
 
-	spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
-	spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
-	spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
+	spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */
+	spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
 				    CPHA=1 */
 
 	/* Dummy byte ensures clock to be low. */
 	for (i = 0; i < 10; i++) {
-		spi->ch[0].SPTDAT = 0xFF;
+		spi->ch[0].sptdat = 0xFF;
 	}
 	spi_wait_transmit_done();
 }
@@ -74,7 +74,8 @@ void spi_wait_transmit_done(void)
 {
 	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
 
-	while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+	while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+		;
 }
 
 
@@ -85,13 +86,13 @@ void tsc2000_write(unsigned short reg, unsigned short data)
 
 	SET_CS_TOUCH();
 	command = reg;
-	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi->ch[0].sptdat = (command & 0x00FF);
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (data & 0xFF00) >> 8;
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0x00FF);
+	spi->ch[0].sptdat = (data & 0x00FF);
 	spi_wait_transmit_done();
 
 	CLR_CS_TOUCH();
@@ -106,19 +107,19 @@ unsigned short tsc2000_read (unsigned short reg)
 	SET_CS_TOUCH();
 	command = 0x8000 | reg;
 
-	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi->ch[0].sptdat = (command & 0x00FF);
 	spi_wait_transmit_done();
 
-	spi->ch[0].SPTDAT = 0xFF;
+	spi->ch[0].sptdat = 0xFF;
 	spi_wait_transmit_done();
-	data = spi->ch[0].SPRDAT;
-	spi->ch[0].SPTDAT = 0xFF;
+	data = spi->ch[0].sprdat;
+	spi->ch[0].sptdat = 0xFF;
 	spi_wait_transmit_done();
 
 	CLR_CS_TOUCH();
-	return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8);
+	return (spi->ch[0].sprdat & 0x0FF) | (data << 8);
 }
 
 
diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h
index 0b6253f..f3cecb9 100644
--- a/board/trab/tsc2000.h
+++ b/board/trab/tsc2000.h
@@ -29,45 +29,49 @@
 #define _TSC2000_H_
 
 /* temperature channel multiplexer definitions */
-#define CON_MUX0		(gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100)
-#define CLR_MUX0		(gpio->PCDAT &= 0x0FFEF)
-#define SET_MUX0		(gpio->PCDAT |= 0x00010)
-
-#define CON_MUX1		(gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400)
-#define CLR_MUX1		(gpio->PCDAT &= 0x0FFDF)
-#define SET_MUX1		(gpio->PCDAT |= 0x00020)
-
-#define CON_MUX1_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000)
-#define CLR_MUX1_ENABLE		(gpio->PCDAT |= 0x00040)
-#define SET_MUX1_ENABLE		(gpio->PCDAT &= 0x0FFBF)
-
-#define CON_MUX2_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000)
-#define CLR_MUX2_ENABLE		(gpio->PCDAT |= 0x00080)
-#define SET_MUX2_ENABLE		(gpio->PCDAT &= 0x0FF7F)
-
-#define CON_MUX3_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000)
-#define CLR_MUX3_ENABLE		(gpio->PCDAT |= 0x00100)
-#define SET_MUX3_ENABLE		(gpio->PCDAT &= 0x0FEFF)
-
-#define CON_MUX4_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000)
-#define CLR_MUX4_ENABLE		(gpio->PCDAT |= 0x00200)
-#define SET_MUX4_ENABLE		(gpio->PCDAT &= 0x0FDFF)
-
-#define CON_SEL_TEMP_V_0	(gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000)
-#define CLR_SEL_TEMP_V_0	(gpio->PCDAT &= 0x0FBFF)
-#define SET_SEL_TEMP_V_0	(gpio->PCDAT |= 0x00400)
-
-#define CON_SEL_TEMP_V_1	(gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000)
-#define CLR_SEL_TEMP_V_1	(gpio->PCDAT &= 0x0F7FF)
-#define SET_SEL_TEMP_V_1	(gpio->PCDAT |= 0x00800)
-
-#define CON_SEL_TEMP_V_2	(gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000)
-#define CLR_SEL_TEMP_V_2	(gpio->PCDAT &= 0x0EFFF)
-#define SET_SEL_TEMP_V_2	(gpio->PCDAT |= 0x01000)
-
-#define CON_SEL_TEMP_V_3	(gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000)
-#define CLR_SEL_TEMP_V_3	(gpio->PCDAT &= 0x0DFFF)
-#define SET_SEL_TEMP_V_3	(gpio->PCDAT |= 0x02000)
+#define CON_MUX0	(gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100)
+#define CLR_MUX0	(gpio->pcdat &= 0x0FFEF)
+#define SET_MUX0	(gpio->pcdat |= 0x00010)
+
+#define CON_MUX1	(gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400)
+#define CLR_MUX1	(gpio->pcdat &= 0x0FFDF)
+#define SET_MUX1	(gpio->pcdat |= 0x00020)
+
+#define CON_MUX1_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE	(gpio->pcdat |= 0x00040)
+#define SET_MUX1_ENABLE	(gpio->pcdat &= 0x0FFBF)
+
+#define CON_MUX2_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE	(gpio->pcdat |= 0x00080)
+#define SET_MUX2_ENABLE	(gpio->pcdat &= 0x0FF7F)
+
+#define CON_MUX3_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE	(gpio->pcdat |= 0x00100)
+#define SET_MUX3_ENABLE	(gpio->pcdat &= 0x0FEFF)
+
+#define CON_MUX4_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE	(gpio->pcdat |= 0x00200)
+#define SET_MUX4_ENABLE	(gpio->pcdat &= 0x0FDFF)
+
+#define CON_SEL_TEMP_V_0	(gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \
+							0x00100000)
+#define CLR_SEL_TEMP_V_0	(gpio->pcdat &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0	(gpio->pcdat |= 0x00400)
+
+#define CON_SEL_TEMP_V_1	(gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \
+		0x00400000)
+#define CLR_SEL_TEMP_V_1	(gpio->pcdat &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1	(gpio->pcdat |= 0x00800)
+
+#define CON_SEL_TEMP_V_2	(gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \
+		0x01000000)
+#define CLR_SEL_TEMP_V_2	(gpio->pcdat &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2	(gpio->pcdat |= 0x01000)
+
+#define CON_SEL_TEMP_V_3	(gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \
+		0x04000000)
+#define CLR_SEL_TEMP_V_3	(gpio->pcdat &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3	(gpio->pcdat |= 0x02000)
 
 /* TSC2000 register definition */
 #define TSC2000_REG_X		((0 << 11) | (0 << 5))
@@ -130,7 +134,7 @@ static inline void SET_CS_TOUCH(void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PDDAT &= 0x5FF;
+	gpio->pddat &= 0x5FF;
 }
 
 
@@ -138,7 +142,7 @@ static inline void CLR_CS_TOUCH(void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PDDAT |= 0x200;
+	gpio->pddat |= 0x200;
 }
 
 #endif	/* _TSC2000_H_ */
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index b7eb8cc..9a2b1ba 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -365,12 +365,12 @@ int vfd_init_clocks (void)
 	/* try to determine display type from the value
 	 * defined by pull-ups
 	 */
-	gpio->PCUP = (gpio->PCUP & 0xFFF0);	/* activate  GPC0...GPC3 pullups */
-	gpio->PCCON = (gpio->PCCON & 0xFFFFFF00);	/* configure GPC0...GPC3 as inputs */
+	gpio->pcup = (gpio->pcup & 0xFFF0); /* activate  GPC0...GPC3 pullups */
+	gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* cfg GPC0...GPC3 inputs */
 	/* allow signals to settle */
 	for (i=0; i<10000; i++)	/* udelay isn't working yet at this point! */
 		__asm__("NOP");
-	vfd_board_id = (~gpio->PCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
+	vfd_board_id = (~gpio->pcdat) & 0x000F;	/* read GPC0...GPC3 port pins */
 
 	VFD_DISABLE;				/* activate blank for the vfd */
 
@@ -381,39 +381,39 @@ int vfd_init_clocks (void)
 		/* If new board revision, then use PWM 3 as cpld-clock */
 		/* Enable 500 Hz timer for fill level sensor to operate properly */
 		/* Configure TOUT3 as functional pin, disable pull-up */
-		gpio->PDCON &= ~0x30000;
-		gpio->PDCON |= 0x20000;
-		gpio->PDUP |= (1 << 8);
+		gpio->pdcon &= ~0x30000;
+		gpio->pdcon |= 0x20000;
+		gpio->pdup |= (1 << 8);
 
 		/* Configure the prescaler */
-		timers->TCFG0 &= ~0xff00;
-		timers->TCFG0 |= 0x0f00;
+		timers->tcfg0 &= ~0xff00;
+		timers->tcfg0 |= 0x0f00;
 
 		/* Select MUX input (divider) for timer3 (1/16) */
-		timers->TCFG1 &= ~0xf000;
-		timers->TCFG1 |= 0x3000;
+		timers->tcfg1 &= ~0xf000;
+		timers->tcfg1 |= 0x3000;
 
 		/* Enable autoreload and set the counter and compare
 		 * registers to values for the 500 Hz clock
 		 * (for a given  prescaler (15) and divider (16)):
 		 * counter = (66000000 / 500) >> 9;
 		 */
-		timers->ch[3].TCNTB = 0x101;
-		timers->ch[3].TCMPB = 0x101 / 2;
+		timers->ch[3].tcntb = 0x101;
+		timers->ch[3].tcmpb = 0x101 / 2;
 
 		/* Start timer */
-		timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
-		timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+		timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->tcon = (timers->tcon | START3) & ~UPDATE3;
 	}
 #endif
 	/* If old board revision, then use vm-signal as cpld-clock */
-	lcd->LCDCON2 = 0x00FFC000;
-	lcd->LCDCON3 = 0x0007FF00;
-	lcd->LCDCON4 = 0x00000000;
-	lcd->LCDCON5 = 0x00000400;
-	lcd->LCDCON1 = 0x00000B75;
+	lcd->lcdcon2 = 0x00FFC000;
+	lcd->lcdcon3 = 0x0007FF00;
+	lcd->lcdcon4 = 0x00000000;
+	lcd->lcdcon5 = 0x00000400;
+	lcd->lcdcon1 = 0x00000B75;
 	/* VM (GPD1) is used as clock for the CPLD */
-	gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
+	gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008;
 
 	return 0;
 }
@@ -485,40 +485,44 @@ int drv_vfd_init(void)
 	 * see manual S3C2400
 	 */
 	/* Stopp LCD-Controller */
-	lcd->LCDCON1 = 0x00000000;
+	lcd->lcdcon1 = 0x00000000;
 	/* frame buffer startadr */
-	lcd->LCDSADDR1 = gd->fb_base >> 1;
+	lcd->lcdsaddr1 = gd->fb_base >> 1;
 	/* frame buffer endadr */
-	lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
-	lcd->LCDSADDR3 = ((256/4));
-	lcd->LCDCON2 = 0x000DC000;
+	lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+	lcd->lcdsaddr3 = ((256/4));
+	lcd->lcdcon2 = 0x000DC000;
 	if(gd->vfd_type == VFD_TYPE_MN11236)
-		lcd->LCDCON2 = 37 << 14;	/* MN11236: 38 lines */
+		lcd->lcdcon2 = 37 << 14;	/* MN11236: 38 lines */
 	else
-		lcd->LCDCON2 = 55 << 14;	/* T119C:   56 lines */
-	lcd->LCDCON3 = 0x0051000A;
-	lcd->LCDCON4 = 0x00000001;
+		lcd->lcdcon2 = 55 << 14;	/* T119C:   56 lines */
+	lcd->lcdcon3 = 0x0051000A;
+	lcd->lcdcon4 = 0x00000001;
 	if (gd->vfd_type && vfd_inv_data)
-		lcd->LCDCON5 = 0x000004C0;
+		lcd->lcdcon5 = 0x000004C0;
 	else
-		lcd->LCDCON5 = 0x00000440;
+		lcd->lcdcon5 = 0x00000440;
 
 	/* Port pins as LCD output */
-	gpio->PCCON =   (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
-	gpio->PDCON =   (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
+	gpio->pccon =   (gpio->pccon & 0xFFFFFF00) | 0x000000AA;
+	gpio->pdcon =   (gpio->pdcon & 0xFFFFFF03) | 0x000000A8;
 
 	/* Synchronize VFD enable with LCD controller to avoid flicker	*/
-	lcd->LCDCON1 = 0x00000B75;			/* Start LCD-Controller	*/
-	while((lcd->LCDCON5 & 0x180000)!=0x100000);	/* Wait for end of VSYNC */
-	while((lcd->LCDCON5 & 0x060000)!=0x040000);	/* Wait for next HSYNC	*/
-	while((lcd->LCDCON5 & 0x060000)==0x040000);
-	while((lcd->LCDCON5 & 0x060000)!=0x000000);
+	lcd->lcdcon1 = 0x00000B75; /* Start LCD-Controller	*/
+	while ((lcd->lcdcon5 & 0x180000) != 0x100000) /* Wait for VSYNC end */
+		;
+	while ((lcd->lcdcon5 & 0x060000) != 0x040000) /* Wait for next HSYNC */
+		;
+	while ((lcd->lcdcon5 & 0x060000) == 0x040000)
+		;
+	while ((lcd->lcdcon5 & 0x060000) != 0x000000)
+		;
 	if(gd->vfd_type)
 		VFD_ENABLE;
 
-	debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
-	debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
-	debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
+	debug("LCDSADDR1: %lX\n", lcd->lcdsaddr1);
+	debug("LCDSADDR2: %lX\n", lcd->lcdsaddr2);
+	debug("LCDSADDR3: %lX\n", lcd->lcdsaddr3);
 
 	return 0;
 }
@@ -532,8 +536,8 @@ void disable_vfd (void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	VFD_DISABLE;
-	gpio->PDCON &= ~0xC;
-	gpio->PDUP  &= ~0x2;
+	gpio->pdcon &= ~0xC;
+	gpio->pdup  &= ~0x2;
 }
 
 /************************************************************************/