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| author | wdenk <wdenk> | 2003-11-17 21:45:27 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-11-17 21:45:27 +0000 |
| commit | b4757cee52597ab5a67c30a1bf2a3208209e1ccb (patch) | |
| tree | 65fb2ebe74d21d96ad26881d73e7a9e5a1f0e849 /board/trab/memsetup.S | |
| parent | 5bb226e821ea3c10c52d768ffab7952204b0f816 (diff) | |
| download | u-boot-imx-b4757cee52597ab5a67c30a1bf2a3208209e1ccb.zip u-boot-imx-b4757cee52597ab5a67c30a1bf2a3208209e1ccb.tar.gz u-boot-imx-b4757cee52597ab5a67c30a1bf2a3208209e1ccb.tar.bz2 | |
Fix flash driver for TRAB board (must use Unlock Bypass Reset command
to exit Unlock Bypass Mode); adjust timings for flash, SRAM and CPLD
Diffstat (limited to 'board/trab/memsetup.S')
| -rw-r--r-- | board/trab/memsetup.S | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/board/trab/memsetup.S b/board/trab/memsetup.S index 0273b94..c93dff6 100644 --- a/board/trab/memsetup.S +++ b/board/trab/memsetup.S @@ -48,29 +48,29 @@ #define BWSCON 0x14000000 /* Bank0 */ -#define B0_Tacs 0x3 /* 4 clk */ -#define B0_Tcos 0x3 /* 4 clk */ -#define B0_Tacc 0x7 /* 14 clk */ -#define B0_Tcoh 0x0 /* 0 clk */ -#define B0_Tah 0x0 /* 0 clk */ +#define B0_Tacs 0x1 /* 1 clk */ +#define B0_Tcos 0x1 /* 1 clk */ +#define B0_Tacc 0x5 /* 8 clk */ +#define B0_Tcoh 0x1 /* 1 clk */ +#define B0_Tah 0x1 /* 1 clk */ #define B0_Tacp 0x0 #define B0_PMC 0x0 /* normal */ /* Bank1 - SRAM */ -#define B1_Tacs 0x0 /* 0 clk */ -#define B1_Tcos 0x0 /* 0 clk */ -#define B1_Tacc 0x7 /* 14 clk */ -#define B1_Tcoh 0x0 /* 0 clk */ -#define B1_Tah 0x0 /* 0 clk */ +#define B1_Tacs 0x1 /* 1 clk */ +#define B1_Tcos 0x1 /* 1 clk */ +#define B1_Tacc 0x5 /* 8 clk */ +#define B1_Tcoh 0x1 /* 1 clk */ +#define B1_Tah 0x1 /* 1 clk */ #define B1_Tacp 0x0 #define B1_PMC 0x0 /* normal */ /* Bank2 - CPLD */ -#define B2_Tacs 0x0 /* 0 clk */ -#define B2_Tcos 0x4 /* 4 clk */ -#define B2_Tacc 0x7 /* 14 clk */ -#define B2_Tcoh 0x4 /* 4 clk */ -#define B2_Tah 0x0 /* 0 clk */ +#define B2_Tacs 0x1 /* 1 clk */ +#define B2_Tcos 0x1 /* 1 clk */ +#define B2_Tacc 0x5 /* 8 clk */ +#define B2_Tcoh 0x1 /* 1 clk */ +#define B2_Tah 0x1 /* 1 clk */ #define B2_Tacp 0x0 #define B2_PMC 0x0 /* normal */ |