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authorWolfgang Denk <wd@pollux.denx.de>2006-07-21 18:51:56 +0200
committerWolfgang Denk <wd@pollux.denx.de>2006-07-21 18:51:56 +0200
commitfc1840e88114ddf1d357435358615a6e0f8e36c9 (patch)
tree7e4afec76db986f3d00cef0a614c5d824b537d67 /board/tqm8xx
parent966083e95f5ba2bf4a1723b19313e69c14b60092 (diff)
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Code cleanup.
Diffstat (limited to 'board/tqm8xx')
-rw-r--r--board/tqm8xx/tqm8xx.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index 06c84f7..6b206f8 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -203,7 +203,7 @@ long int initdram (int board_type)
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
(board_type != 'M') &&
- (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
udelay (1);
memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
@@ -220,8 +220,7 @@ long int initdram (int board_type)
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
udelay (1000);
@@ -229,8 +228,7 @@ long int initdram (int board_type)
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
udelay(1000);
@@ -239,8 +237,7 @@ long int initdram (int board_type)
/*
* try 10 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
#else
size10 = 0;