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authorWolfgang Denk <wd@pollux.denx.de>2006-08-07 23:21:52 +0200
committerWolfgang Denk <wd@pollux.denx.de>2006-08-07 23:21:52 +0200
commit98280e3d431db77d92219438b8840853bd7cb412 (patch)
treef771fe8d5086d32cda26a0b8d16f9b95e761838e /board/tqm8xx
parent99d70e3a47affb9bae041a2caece7cd516e213b3 (diff)
parent6587f7e1e98bfcb7910a47bae2eb51e9a5fbd4da (diff)
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Merge with /home/wd/git/u-boot/master
Diffstat (limited to 'board/tqm8xx')
-rw-r--r--board/tqm8xx/flash.c5
-rw-r--r--board/tqm8xx/tqm8xx.c22
2 files changed, 16 insertions, 11 deletions
diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c
index ab57ee5..db0a7e5 100644
--- a/board/tqm8xx/flash.c
+++ b/board/tqm8xx/flash.c
@@ -33,12 +33,13 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
+ && !defined(CONFIG_TQM885D)
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_2_CLK | OR_EHTR | OR_BI)
# endif
-#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
#ifndef CFG_ENV_ADDR
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index b292231..6b206f8 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -119,6 +119,10 @@ int checkboard (void)
gd->board_type = 'M';
}
+ if ((*(s + 6) == 'D')) { /* a TQM885D type */
+ gd->board_type = 'D';
+ }
+
for (; *s; ++s) {
if (*s == ' ')
break;
@@ -178,7 +182,8 @@ long int initdram (int board_type)
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
- (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
}
@@ -197,7 +202,8 @@ long int initdram (int board_type)
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
- (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
udelay (1);
memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
@@ -214,8 +220,7 @@ long int initdram (int board_type)
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
udelay (1000);
@@ -223,8 +228,7 @@ long int initdram (int board_type)
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
udelay(1000);
@@ -233,8 +237,7 @@ long int initdram (int board_type)
/*
* try 10 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
#else
size10 = 0;
@@ -255,7 +258,8 @@ long int initdram (int board_type)
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
- (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
/*
* Check Bank 1 Memory Size
* use current column settings