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authorJens Gehrlein <jens.gehrlein@tqs.de>2007-09-26 17:55:54 +0200
committerWolfgang Denk <wd@denx.de>2007-12-27 01:59:50 +0100
commit22d1a56cbfb0bff34f477b4db6a55d076d829b83 (patch)
treeb8206a0016a00d0d13564b2ff22c080cadf9f762 /board/tqm8xx/tqm8xx.c
parentb988b8cd443989be65161888eea0127ad03f846f (diff)
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TQM885D: Exchanged SDRAM timing by a more relaxed timing.
CAS-Latency=2, Write Recovery Time tWR=2 The max. supported bus frequency is 66 MHz. Therefore, changed threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz. Signed-off-by: Martin Krause <martin.krause@tqs.de>
Diffstat (limited to 'board/tqm8xx/tqm8xx.c')
-rw-r--r--board/tqm8xx/tqm8xx.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index cebdcc0..06bf5f8 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -37,6 +37,7 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFFFFF
+/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
const uint sdram_table[] =
{
/*
@@ -63,14 +64,14 @@ const uint sdram_table[] =
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
- 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
+ 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
- _NOT_USED_,
+ 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
@@ -83,7 +84,7 @@ const uint sdram_table[] =
/*
* Exception. (Offset 3c in UPMA RAM)
*/
- 0x7FFFFC07, /* last */
+ 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};