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| author | Jon Loeliger <jdl@freescale.com> | 2006-08-09 13:36:54 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2006-08-09 13:36:54 -0500 |
| commit | 281f69ede28cd3d8be5d62a96b5a0b73e6065858 (patch) | |
| tree | 8f1a0f42ce7d9c66d0ff2ecf93c9b069cbc68cc0 /board/tqm834x/tqm834x.c | |
| parent | 870cbeaa45ccdbd6566882741da9f82433bd4a86 (diff) | |
| parent | 6587f7e1e98bfcb7910a47bae2eb51e9a5fbd4da (diff) | |
| download | u-boot-imx-281f69ede28cd3d8be5d62a96b5a0b73e6065858.zip u-boot-imx-281f69ede28cd3d8be5d62a96b5a0b73e6065858.tar.gz u-boot-imx-281f69ede28cd3d8be5d62a96b5a0b73e6065858.tar.bz2 | |
Merge branch 'wd'
Diffstat (limited to 'board/tqm834x/tqm834x.c')
| -rw-r--r-- | board/tqm834x/tqm834x.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index b5c12e3..41b34cc 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -406,4 +406,30 @@ static void set_ddr_config(void) { (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); SYNC; + + /* Workaround for DDR6 Erratum + * see MPC8349E Device Errata Rev.8, 2/2006 + * This workaround influences the MPC internal "input enables" + * dependent on CAS latency and MPC revision. According to errata + * sheet the internal reserved registers for this workaround are + * not available from revision 2.0 and up. + */ + + /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 + * (0x200) + */ + if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { + + /* There is a internal reserved register at IMMRBAR+0x2F00 + * which has to be written with a certain value defined by + * errata sheet. + */ + u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00); + +#if defined(DDR_CASLAT_20) + *reserved_p = 0x201c0000; +#else + *reserved_p = 0x202c0000; +#endif + } } |