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authorWolfgang Grandegger <wg@grandegger.com>2009-02-11 18:38:25 +0100
committerAndy Fleming <afleming@freescale.com>2009-02-16 18:06:02 -0600
commit080408fdc71706adcb883d22125637c54f6010b1 (patch)
tree9ddd7a5f6ac5a1a4e43b66b56674b4a63b0d1a3e /board/tqc
parentdc5f55d636d7bf21ba17758fac4b929ec4c059f2 (diff)
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MPC85xx: TQM8548: use cache for AG and BE variants
This patch makes accesses to the system memory cachable by removing the caching-inhibited and guarded flags from the relevant TLB entries for the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards are configured similarly. This results in a big averall performace improvement. TFTP downloads, NAND Flash accesses, kernel boots, etc. are much faster. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Diffstat (limited to 'board/tqc')
-rw-r--r--board/tqc/tqm85xx/tlb.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index ad96dd1..71fe3ab 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -128,12 +128,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
* Without SPD EEPROM configured DDR, this must be setup manually.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#else
/*