mpc83xx: convert all remaining boards over to 83XX_GENERIC_PCI

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

2 files changed, 35 insertions, 182 deletions

diff --git a/board/tqc/tqm834x/Makefile b/board/tqc/tqm834x/Makefile
index 8889726..011e631 100644
--- a/board/tqc/tqm834x/Makefile
+++ b/board/tqc/tqm834x/Makefile
@@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o pci.o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
 
+COBJS   := $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
index 6c113e3..fcf4379 100644
--- a/board/tqc/tqm834x/pci.c
+++ b/board/tqc/tqm834x/pci.c
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,45 +24,37 @@
  */
 
 #include <asm/mmu.h>
+#include <asm/io.h>
 #include <common.h>
-#include <asm/global_data.h>
+#include <mpc83xx.h>
 #include <pci.h>
-#include <asm/mpc8349_pci.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_PCI
-
-/* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_tqm834x_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
-	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-				     PCI_ENET0_MEMADDR,
-				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
-		}
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
 	},
-	{}
-};
-#endif
-
-static struct pci_controller pci1_hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table:pci_tqm834x_config_table,
-#endif
 };
 
-
-/**************************************************************************
+/*
  * pci_init_board()
  *
  * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
@@ -76,30 +69,15 @@ static struct pci_controller pci1_hose = {
 void
 pci_init_board(void)
 {
-	volatile immap_t *	immr;
-	volatile clk83xx_t *	clk;
-	volatile law83xx_t *	pci_law;
-	volatile pot83xx_t *	pci_pot;
-	volatile pcictrl83xx_t *	pci_ctrl;
-	volatile pciconf83xx_t *	pci_conf;
-	u16 reg16;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
 	u32 reg32;
-	struct	pci_controller * hose;
-
-	immr = (immap_t *)CONFIG_SYS_IMMR;
-	clk = (clk83xx_t *)&immr->clk;
-	pci_law = immr->sysconf.pcilaw;
-	pci_pot = immr->ios.pot;
-	pci_ctrl = immr->pci_ctrl;
-	pci_conf = immr->pci_conf;
-
-	hose = &pci1_hose;
 
 	/*
 	 * Configure PCI controller and PCI_CLK_OUTPUT
-	 */
-
-	/*
+	 *
 	 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
 	 * line actually used for clocking all external PCI devices in TQM83xx.
 	 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
@@ -125,141 +103,14 @@ pci_init_board(void)
 	clk->occr = reg32;
 	udelay(2000);
 
-	/*
-	 * Release PCI RST Output signal
-	 */
-	pci_ctrl[0].gcr = 0;
-	udelay(2000);
-	pci_ctrl[0].gcr = 1;
-	udelay(2000);
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
+	/* Configure PCI Local Access Windows */
 	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
 
 	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
 
-	/*
-	 * Configure PCI Outbound Translation Windows
-	 */
-
-	/* PCI1 mem space */
-	pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
-	pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
-
-	/* PCI1 IO space */
-	pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
-	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-
-	/*
-	 * Configure PCI Inbound Translation Windows
-	 */
-
-	/* we need RAM mapped to PCI space for the devices to
-	 * access main memory */
-	pci_ctrl[0].pitar1 = 0x0;
-	pci_ctrl[0].pibar1 = 0x0;
-	pci_ctrl[0].piebar1 = 0x0;
-	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		       CONFIG_SYS_PCI1_MEM_BASE,
-		       CONFIG_SYS_PCI1_MEM_PHYS,
-		       CONFIG_SYS_PCI1_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		       CONFIG_SYS_PCI1_IO_BASE,
-		       CONFIG_SYS_PCI1_IO_PHYS,
-		       CONFIG_SYS_PCI1_IO_SIZE,
-		       PCI_REGION_IO);
-
-	/* System memory space */
-	pci_set_region(hose->regions + 2,
-		       CONFIG_PCI_SYS_MEM_BUS,
-		       CONFIG_PCI_SYS_MEM_PHYS,
-		       CONFIG_PCI_SYS_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	hose->region_count = 3;
-
-	pci_setup_indirect(hose,
-			   (CONFIG_SYS_IMMR+0x8300),
-			   (CONFIG_SYS_IMMR+0x8304));
-
-	pci_register_hose(hose);
-
-	/*
-	 * Write to Command register
-	 */
-	reg16 = 0xff;
-	pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
-					&reg16);
-	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
-					reg16);
-
-	/*
-	 * Clear non-reserved bits in status register.
-	 */
-	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
-					0xffff);
-	pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
-					0x80);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-	/*
-	 * Hose scan.
-	 */
-	hose->last_busno = pci_hose_scan(hose);
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
-	int nodeoffset;
-	int tmp[2];
-	const char *path;
-
-	nodeoffset = fdt_path_offset(blob, "/aliases");
-	if (nodeoffset >= 0) {
-		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
-		if (path) {
-			tmp[0] = cpu_to_be32(pci1_hose.first_busno);
-			tmp[1] = cpu_to_be32(pci1_hose.last_busno);
-			do_fixup_by_path(blob, path, "bus-range",
-				&tmp, sizeof(tmp), 1);
-
-			tmp[0] = cpu_to_be32(gd->pci_clk);
-			do_fixup_by_path(blob, path, "clock-frequency",
-				&tmp, sizeof(tmp[0]), 1);
-		}
-#ifdef CONFIG_MPC83XX_PCI2
-		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
-		if (path) {
-			tmp[0] = cpu_to_be32(pci2_hose.first_busno);
-			tmp[1] = cpu_to_be32(pci2_hose.last_busno);
-			do_fixup_by_path(blob, path, "bus-range",
-				&tmp, sizeof(tmp), 1);
+	udelay(2000);
 
-			tmp[0] = cpu_to_be32(gd->pci_clk);
-			do_fixup_by_path(blob, path, "clock-frequency",
-				&tmp, sizeof(tmp[0]), 1);
-		}
-#endif
-	}
+	mpc83xx_pci_init(1, reg, 0);
 }
-#endif /* CONFIG_OF_LIBFDT */
-#endif /* CONFIG_PCI */