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author | Becky Bruce <beckyb@kernel.crashing.org> | 2010-06-17 11:37:20 -0500 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2010-07-16 10:55:09 -0500 |
commit | f51cdaf19141151ce2b40d562a468605340f2315 (patch) | |
tree | 60b51af79796f061d119f2839d101f9584964dfc /board/tqc/tqm85xx/tqm85xx.c | |
parent | 0914f4832887341ee073d2d2bfbada69a6872548 (diff) | |
download | u-boot-imx-f51cdaf19141151ce2b40d562a468605340f2315.zip u-boot-imx-f51cdaf19141151ce2b40d562a468605340f2315.tar.gz u-boot-imx-f51cdaf19141151ce2b40d562a468605340f2315.tar.bz2 |
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/tqc/tqm85xx/tqm85xx.c')
-rw-r--r-- | board/tqc/tqm85xx/tqm85xx.c | 35 |
1 files changed, 17 insertions, 18 deletions
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 8c9d586..fc2a6cb 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -269,8 +269,6 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - /* * Adjust flash start and offset to detected values */ @@ -281,26 +279,27 @@ int misc_init_r (void) * Recalculate CS configuration if second FLASH bank is available */ if (flash_info[0].size > 0) { - memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | - (CONFIG_SYS_OR1_PRELIM & 0x00007fff); - memctl->br1 = gd->bd->bi_flashstart | - (CONFIG_SYS_BR1_PRELIM & 0x00007fff); + set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) | + (CONFIG_SYS_OR1_PRELIM & 0x00007fff)); + set_lbc_br(1, gd->bd->bi_flashstart | + (CONFIG_SYS_BR1_PRELIM & 0x00007fff)); /* * Re-check to get correct base address for bank 1 */ flash_get_size (gd->bd->bi_flashstart, 0); } else { - memctl->or1 = 0; - memctl->br1 = 0; + set_lbc_or(1, 0); + set_lbc_br(1, 0); } /* * If bank 1 is equipped, bank 0 is mapped after bank 1 */ - memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | - (CONFIG_SYS_OR0_PRELIM & 0x00007fff); - memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | - (CONFIG_SYS_BR0_PRELIM & 0x00007fff); + set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) | + (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); + set_lbc_br(0, gd->bd->bi_flashstart | + (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); + /* * Re-check to get correct base address for bank 0 */ @@ -341,7 +340,7 @@ int misc_init_r (void) */ static void upmc_write (u_char addr, uint val) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; out_be32 (&lbc->mdr, val); @@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val) uint get_lbc_clock (void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; sys_info_t sys_info; ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; @@ -386,7 +385,7 @@ uint get_lbc_clock (void) void local_bus_init (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint lbc_mhz = get_lbc_clock () / 1000000; #ifdef CONFIG_MPC8548 @@ -502,10 +501,10 @@ void local_bus_init (void) * set if Local Bus Clock is > 83 MHz. */ if (lbc_mhz > 83) - out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); + set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); else - out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN); - out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN); + set_lbc_or(2, CONFIG_SYS_OR2_CAN); + set_lbc_br(2, CONFIG_SYS_BR2_CAN); /* LGPL4 is UPWAIT */ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); |