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| author | Wolfgang Grandegger <wg@grandegger.com> | 2008-06-05 13:12:05 +0200 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-06-10 23:59:44 -0500 |
| commit | d9ee843d54c54776e1fdb86336ce554906a87331 (patch) | |
| tree | 3b0d55c9ed3680defecf3b345ff19305cb315e0f /board/tqc/tqm85xx/tlb.c | |
| parent | 518d5cfe72916323c746af1647764459914f555f (diff) | |
| download | u-boot-imx-d9ee843d54c54776e1fdb86336ce554906a87331.zip u-boot-imx-d9ee843d54c54776e1fdb86336ce554906a87331.tar.gz u-boot-imx-d9ee843d54c54776e1fdb86336ce554906a87331.tar.bz2 | |
TQM85xx: Support for Intel 82527 compatible CAN controller
This patch adds initialization of the UPMC RAM to support up to two
Intel 82527 compatible CAN controller on the TQM85xx modules.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Diffstat (limited to 'board/tqc/tqm85xx/tlb.c')
| -rw-r--r-- | board/tqc/tqm85xx/tlb.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 3e29062..dc36201 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -95,6 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 16M PCI1 IO + * 0xe3000000 16M CAN */ SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |