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| author | Wolfgang Grandegger <wg@grandegger.com> | 2009-02-11 18:38:24 +0100 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2009-02-16 18:06:01 -0600 |
| commit | dc5f55d636d7bf21ba17758fac4b929ec4c059f2 (patch) | |
| tree | 1c1956fea72e5d5da29f59559b2c6634df819bcf /board/tqc/tqm85xx/tlb.c | |
| parent | 88b0e88d186479349e5a2b771e82775109e10fb4 (diff) | |
| download | u-boot-imx-dc5f55d636d7bf21ba17758fac4b929ec4c059f2.zip u-boot-imx-dc5f55d636d7bf21ba17758fac4b929ec4c059f2.tar.gz u-boot-imx-dc5f55d636d7bf21ba17758fac4b929ec4c059f2.tar.bz2 | |
MPC85xx: TQM8548_AG: add 1 GiB DDR2-SDRAM configuration
This patch add support for the 1 GiB DDR2-SDRAM on the TQM8548_AG
module.
Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Diffstat (limited to 'board/tqc/tqm85xx/tlb.c')
| -rw-r--r-- | board/tqc/tqm85xx/tlb.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 16b102d..ad96dd1 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -121,12 +121,25 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), +#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE) + /* + * TLB 7+8: 2G DDR, cache enabled + * 0x00000000 2G DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + */ + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_1G, 1), + + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_1G, 1), +#else /* * TLB 7+8: 512M DDR, cache disabled (needed for memory test) * 0x00000000 512M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. */ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, @@ -136,7 +149,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), - +#endif #ifdef CONFIG_PCIE1 /* * TLB 9: 16M Non-cacheable, guarded |