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authorWolfgang Denk <wd@denx.de>2009-07-23 00:52:30 +0200
committerWolfgang Denk <wd@denx.de>2009-07-23 00:52:30 +0200
commit05c37340183ff097b29d66e8d7862fc21162bc6e (patch)
tree0c2c940665a7333620c668855524536672eb46cf /board/tqc/tqm85xx/sdram.c
parent48677a1ef5f82adca49145a7baf11ece77f51945 (diff)
parent5a625149dbe14d381df454c459c6aaf27d59af20 (diff)
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Merge branch 'master' of /home/wd/git/u-boot/custodians
Diffstat (limited to 'board/tqc/tqm85xx/sdram.c')
-rw-r--r--board/tqc/tqm85xx/sdram.c33
1 files changed, 3 insertions, 30 deletions
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 6d73a88..503c5e5 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -374,31 +374,6 @@ long int sdram_setup (int casl)
return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
}
-void board_add_ram_info (int use_default)
-{
- int casl;
-
- if (use_default)
- casl = CONFIG_DDR_DEFAULT_CL;
- else
- casl = cas_latency ();
-
- puts (" (CL=");
- switch (casl) {
- case 20:
- puts ("2)");
- break;
-
- case 25:
- puts ("2.5)");
- break;
-
- case 30:
- puts ("3)");
- break;
- }
-}
-
phys_size_t initdram (int board_type)
{
long dram_size = 0;
@@ -438,11 +413,9 @@ phys_size_t initdram (int board_type)
/*
* Try again with default CAS latency
*/
- puts ("Problem with CAS lantency");
- board_add_ram_info (1);
- puts (", using default CL!\n");
- casl = CONFIG_DDR_DEFAULT_CL;
- dram_size = sdram_setup (casl);
+ printf ("Problem with CAS lantency, using default CL %d/10!\n",
+ CONFIG_DDR_DEFAULT_CL);
+ dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL);
puts (" ");
}