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| author | Wolfgang Grandegger <wg@grandegger.com> | 2008-06-05 13:12:09 +0200 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-06-11 00:05:08 -0500 |
| commit | 1c2deff22cd6e2bf0e618fd6e09ca3eec5a8d051 (patch) | |
| tree | 55883ded24813be6cd7ddf5e30894357f3c7266b /board/tqc/tqm85xx/law.c | |
| parent | b9e8078bb3f3c48111a7081e27279938c3a445e1 (diff) | |
| download | u-boot-imx-1c2deff22cd6e2bf0e618fd6e09ca3eec5a8d051.zip u-boot-imx-1c2deff22cd6e2bf0e618fd6e09ca3eec5a8d051.tar.gz u-boot-imx-1c2deff22cd6e2bf0e618fd6e09ca3eec5a8d051.tar.bz2 | |
TQM85xx: NAND support via local bus UPMB
This patch adds support for NAND FLASH on the TQM8548. It is disabled by
default and can be enabled for the TQM8548 modules. It is now based on
the re-written FSL NAND UPM driver. A patch has been posted earlier today
with the subject:
"NAND FSL UPM: driver re-write using the hwcontrol callback"
Note that the R/B pin is not supported by that module requiring to use
the specified maximum delay time.
Note: With NAND support enabled the size of the U-Boot image exceeds
256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk,
doubling the image size :-(.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Diffstat (limited to 'board/tqc/tqm85xx/law.c')
| -rw-r--r-- | board/tqc/tqm85xx/law.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index bec1ed5..914ce68 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -35,7 +35,7 @@ * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff CAN 16M + * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M * 0xef00_0000 0xefff_ffff PCI express IO 16M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * @@ -54,9 +54,9 @@ struct law_entry law_table[] = { #else /* !CONFIG_PCIE1 */ SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif /* CONFIG_PCIE1 */ -#ifdef CONFIG_CAN_DRIVER +#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), -#endif /* CONFIG_CAN_DRIVER */ +#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ #ifdef CONFIG_PCIE1 SET_LAW_ENTRY (7, CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), #endif /* CONFIG_PCIE */ |