TQM: move TQM boards to board/tqc

Move all TQM board directories to the vendor specific directory "tqc"
for modules from TQ-Components GmbH (http://www.tqc.de).

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>

4 files changed, 937 insertions, 0 deletions

diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile
new file mode 100644
index 0000000..61221fd
--- /dev/null
+++ b/board/tqc/tqm8260/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../tqm8xx/)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/tqc/tqm8260/config.mk b/board/tqc/tqm8260/config.mk
new file mode 100644
index 0000000..1fe9952
--- /dev/null
+++ b/board/tqc/tqm8260/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8260 boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c
new file mode 100644
index 0000000..056fe81
--- /dev/null
+++ b/board/tqc/tqm8260/flash.c
@@ -0,0 +1,488 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD devices on the TQM8260 board
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+		V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
+		V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	/* Write auto select command sequence and test FLASH answer */
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
+
+	flashtest_h = V_ULONG (baseaddr);	/* manufacturer ID     */
+	flashtest_l = V_ULONG (baseaddr + 4);
+
+	switch ((int) flashtest_h) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash     */
+	}
+
+	flashtest_h = V_ULONG (baseaddr + 8);	/* device ID           */
+	flashtest_l = V_ULONG (baseaddr + 12);
+	if (flashtest_h != flashtest_l) {
+		info->flash_id = FLASH_UNKNOWN;
+	} else {
+		switch (flashtest_h) {
+		case AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_DL322T:
+			info->flash_id += FLASH_AMDL322T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL322B:
+			info->flash_id += FLASH_AMDL322B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323T:
+			info->flash_id += FLASH_AMDL323T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323B:
+			info->flash_id += FLASH_AMDL323B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_LV640U:
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x02000000;
+			break;			/* 4 * 8 MB = 32 MB */
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);		/* no or unknown flash     */
+		}
+	}
+
+	if (flashtest_h == AMD_ID_LV640U) {
+
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+
+	} else if (info->flash_id & FLASH_BTYPE) {
+
+		/* set up sector start adress table (bottom sector type) */
+		info->start[0] = baseaddr + 0x00000000;
+		info->start[1] = baseaddr + 0x00010000;
+		info->start[2] = baseaddr + 0x00018000;
+		info->start[3] = baseaddr + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+		}
+
+	} else {
+
+		/* set up sector start adress table (top sector type) */
+		i = info->sector_count - 1;
+		info->start[i--] = baseaddr + info->size - 0x00010000;
+		info->start[i--] = baseaddr + info->size - 0x00018000;
+		info->start[i--] = baseaddr + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = baseaddr + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
+			(V_ULONG (info->start[i] + 20) & 0x00010001)) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset ();
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		printf ("29LV800T (8 M, top sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("29LV800T (8 M, bottom sector)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("29LV160T (16 M, top sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("29LV160B (16 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:
+		printf ("29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:
+		printf ("29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:
+		printf ("29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AM640U:
+		printf ("29LV640D (64 M, uniform sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			V_ULONG (info->start[sect]) = 0x00300030;
+			V_ULONG (info->start[sect] + 4) = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
+	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
+	{
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);		/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
+		if ((rc = write_dword (info, dp, bb)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword (info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
+	}
+	return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+	ulong start, cl, ch;
+	int flag, i;
+
+	for (ch = 0, i = 0; i < 4; i++)
+		ch = (ch << 8) + *pdata++;	/* high word    */
+	for (cl = 0, i = 0; i < 4; i++)
+		cl = (cl << 8) + *pdata++;	/* low word */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & ch) != ch
+		|| (*((vu_long *) (dest + 4)) & cl) != cl) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest) = ch;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest + 4) = cl;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
+		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c
new file mode 100644
index 0000000..736c410
--- /dev/null
+++ b/board/tqc/tqm8260/tqm8260.c
@@ -0,0 +1,368 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "TQM82", 5)) {
+		puts ("### No HW ID - assuming TQM8260\n");
+		return (0);
+	}
+
+	puts (str);
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	long size8, size9;
+#endif
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#if 0							/* Just for debugging */
+#define	prt_br_or(brX,orX) do {				\
+    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
+    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
+    printf ("\n"					\
+	    #brX " 0x%08x  " #orX " 0x%08x "		\
+	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
+	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
+	start, start+sizem, (sizem+1)>>20);		\
+    } while (0)
+	prt_br_or (br0, or0);
+	prt_br_or (br1, or1);
+	prt_br_or (br2, or2);
+	prt_br_or (br3, or3);
+#endif
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+					  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
+					  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL - %ld MB, ", psize >> 20);
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+						  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL - %ld MB, ", psize >> 20);
+	}
+
+	/* Local SDRAM setup:
+	 */
+#ifdef CFG_INIT_LOCAL_SDRAM
+	memctl->memc_lsrt = CFG_LSRT;
+	size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+	size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+
+	if (size8 < size9) {
+		lsize = size9;
+		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
+	} else {
+		lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+						  (uchar *) SDRAM_BASE2_PRELIM);
+		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
+	}
+
+#if 0
+	/* Set up BR2 so that the local SDRAM goes
+	 * right after the 60x SDRAM
+	 */
+	memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
+			(CFG_SDRAM_BASE + psize);
+#endif
+#endif /* CFG_INIT_LOCAL_SDRAM */
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+/* ------------------------------------------------------------------------- */