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authorChris Lalancette <clalancette@gmail.com>2011-12-13 09:41:12 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-12-19 17:52:44 +0100
commitdf65a3fe3504930d5a89699e9903554f4605b098 (patch)
treeb3205d378f7b6af700485b7ef3bfaf985b3ba3b9 /board/ti
parentc005d6b193c4d98159181576c52747f92df977f2 (diff)
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omap4_panda: Initialize the USB phy
During misc_init_r, make sure to setup the clocks properly for the USB hub on the pandaboard. With this in place, the USB hub and the ethernet works on the pandaboard. Signed-off-by: Chris Lalancette <clalancette@gmail.com> Acked-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'board/ti')
-rw-r--r--board/ti/panda/panda.c59
1 files changed, 59 insertions, 0 deletions
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index b4271fb..fc8c0b4 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -24,15 +24,21 @@
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/gpio.h>
#include "panda_mux_data.h"
+#define PANDA_ULPI_PHY_TYPE_GPIO 182
+
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
"Board: OMAP4 Panda\n"
};
+struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
+
/**
* @brief board_init
*
@@ -62,6 +68,59 @@ int board_eth_init(bd_t *bis)
*/
int misc_init_r(void)
{
+ int phy_type;
+ u32 auxclk, altclksrc;
+
+ /* EHCI is not supported on ES1.0 */
+ if (omap_revision() == OMAP4430_ES1_0)
+ return 0;
+
+ gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
+ phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+
+ if (phy_type == 1) {
+ /* ULPI PHY supplied by auxclk3 derived from sys_clk */
+ debug("ULPI PHY supplied by auxclk3\n");
+
+ auxclk = readl(&scrm->auxclk3);
+ /* Select sys_clk */
+ auxclk &= ~AUXCLK_SRCSELECT_MASK;
+ auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
+ /* Set the divisor to 2 */
+ auxclk &= ~AUXCLK_CLKDIV_MASK;
+ auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
+ /* Request auxilary clock #3 */
+ auxclk |= AUXCLK_ENABLE_MASK;
+
+ writel(auxclk, &scrm->auxclk3);
+ } else {
+ /* ULPI PHY supplied by auxclk1 derived from PER dpll */
+ debug("ULPI PHY supplied by auxclk1\n");
+
+ auxclk = readl(&scrm->auxclk1);
+ /* Select per DPLL */
+ auxclk &= ~AUXCLK_SRCSELECT_MASK;
+ auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
+ /* Set the divisor to 16 */
+ auxclk &= ~AUXCLK_CLKDIV_MASK;
+ auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
+ /* Request auxilary clock #3 */
+ auxclk |= AUXCLK_ENABLE_MASK;
+
+ writel(auxclk, &scrm->auxclk1);
+ }
+
+ altclksrc = readl(&scrm->altclksrc);
+
+ /* Activate alternate system clock supplier */
+ altclksrc &= ~ALTCLKSRC_MODE_MASK;
+ altclksrc |= ALTCLKSRC_MODE_ACTIVE;
+
+ /* enable clocks */
+ altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
+
+ writel(altclksrc, &scrm->altclksrc);
+
return 0;
}