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authorLokesh Vutla <lokeshvutla@ti.com>2014-02-18 07:31:57 -0500
committerTom Rini <trini@ti.com>2014-03-04 09:42:07 -0500
commite27f2dd721d8121177cb32a63684557fa625d4bf (patch)
treeae8a6a5e1b064ced5d268b61a193dbd3617b589f /board/ti
parent8feb37b9beefd4ba38227a837b6d7b3f5821b90c (diff)
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ARM: AM4372: Update EMIF registers for DDR3
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD registers. In EMIF_PHY_CTRL: Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the read latency expected will be CL+3 as per tests from HW folks. Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug purpose. With out this resume is not working(Still waiting for PHY team to come back for better explanation). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/ti')
-rw-r--r--board/ti/am43xx/board.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 0c9f0ef..7a28063 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -206,7 +206,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074BE4,
.temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E084008,
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00400040,
.emif_ddr_ext_phy_ctrl_3 = 0x00400040,