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authorLokesh Vutla <lokeshvutla@ti.com>2013-12-10 15:02:21 +0530
committerTom Rini <trini@ti.com>2013-12-18 21:14:18 -0500
commit965de8b91bddd1f5967240d1d44005719b09dd5e (patch)
treedbcbdffdaaf14e8ace3eb1a911f27ace0352bbc6 /board/ti/ti816x/evm.c
parentcf04d0326bd1e24909cfe644c0c8676440a915b1 (diff)
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ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/ti/ti816x/evm.c')
-rw-r--r--board/ti/ti816x/evm.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index a53859e..b6bf162 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -191,22 +191,26 @@ void sdram_init(void)
if (CONFIG_TI816X_USE_EMIF0) {
ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
- config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
+ config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
+ 0);
}
if (CONFIG_TI816X_USE_EMIF1) {
ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
- config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
+ config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
+ 1);
}
#endif
#ifdef CONFIG_TI816X_EVM_DDR3
if (CONFIG_TI816X_USE_EMIF0)
- config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
+ config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
+ 0);
if (CONFIG_TI816X_USE_EMIF1)
- config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
+ config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
+ 1);
#endif
}
#endif /* CONFIG_SPL_BUILD */