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author | Tom Rix <Tom.Rix@windriver.com> | 2009-10-17 12:41:06 -0500 |
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committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-24 09:55:25 -0500 |
commit | e63e5904b48528f3f3cc98317df6fc62fab25bf9 (patch) | |
tree | 6c700f252742d34368fc58f919e1238c8b7cbe27 /board/ti/sdp3430/sdp.c | |
parent | a4474ff8629be5f28aefb8a9f48d4411d62fb0d2 (diff) | |
download | u-boot-imx-e63e5904b48528f3f3cc98317df6fc62fab25bf9.zip u-boot-imx-e63e5904b48528f3f3cc98317df6fc62fab25bf9.tar.gz u-boot-imx-e63e5904b48528f3f3cc98317df6fc62fab25bf9.tar.bz2 |
TI OMAP3 SDP3430: Initial Support
Start of support of
Texas Instruments Software Development Platform(SDP)
for OMAP3430 - SDP3430
Highlights of this platform are:
Flash Memory devices:
Sibley NOR, Micron 8bit NAND and OneNAND
Connectivity:
3 UARTs and expanded 4 UART ports + IrDA
Ethernet, USB
Other peripherals:
TWL5030 PMIC+Audio+Keypad
VGA display
Expansion ports:
Memory devices plugin boards (PISMO)
Connectivity board for GPS,WLAN etc.
Completely configurable boot sequence and device mapping
etc.
Support default jumpering and:
- UART1/ttyS0 console(legacy sdp3430 u-boot)
- UART3/ttyS2 console (matching other boards,
and SDP HW docs)
- Ethernet
- mmc0
- NOR boot
Currently the UART1 is enabled by default. for
compatibility with other OMAP3 u-boot platforms,
enable the #define of CONSOLE_J9.
Conflicts:
Makefile
Fixed the conflict with smdkc100_config by moving omap_sdp3430_config
to it is alphabetically sorted location above zoom1.
Signed-off-by: David Brownell <david-b@pacbell.net>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Diffstat (limited to 'board/ti/sdp3430/sdp.c')
-rw-r--r-- | board/ti/sdp3430/sdp.c | 204 |
1 files changed, 204 insertions, 0 deletions
diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c new file mode 100644 index 0000000..40cf26f --- /dev/null +++ b/board/ti/sdp3430/sdp.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "sdp.h" + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 SDP3430 board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#elif defined(CONFIG_ENV_IS_IN_NAND) + "NAND", +#else + "NOR", +#endif +}; + +/* Timing definitions for GPMC controller for Sibley NOR */ +static const u32 gpmc_sdp_nor[] = { + SDP3430_NOR_GPMC_CONF1, + SDP3430_NOR_GPMC_CONF2, + SDP3430_NOR_GPMC_CONF3, + SDP3430_NOR_GPMC_CONF4, + SDP3430_NOR_GPMC_CONF5, + SDP3430_NOR_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* + * Timing definitions for GPMC controller for Debug Board + * Debug board contains access to ethernet and DIP Switch setting + * information etc. + */ +static const u32 gpmc_sdp_debug[] = { + SDP3430_DEBUG_GPMC_CONF1, + SDP3430_DEBUG_GPMC_CONF2, + SDP3430_DEBUG_GPMC_CONF3, + SDP3430_DEBUG_GPMC_CONF4, + SDP3430_DEBUG_GPMC_CONF5, + SDP3430_DEBUG_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* Timing defintions for GPMC OneNAND */ +static const u32 gpmc_sdp_onenand[] = { + SDP3430_ONENAND_GPMC_CONF1, + SDP3430_ONENAND_GPMC_CONF2, + SDP3430_ONENAND_GPMC_CONF3, + SDP3430_ONENAND_GPMC_CONF4, + SDP3430_ONENAND_GPMC_CONF5, + SDP3430_ONENAND_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* GPMC definitions for GPMC NAND */ +static const u32 gpmc_sdp_nand[] = { + SDP3430_NAND_GPMC_CONF1, + SDP3430_NAND_GPMC_CONF2, + SDP3430_NAND_GPMC_CONF3, + SDP3430_NAND_GPMC_CONF4, + SDP3430_NAND_GPMC_CONF5, + SDP3430_NAND_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* gpmc_cfg is initialized by gpmc_init and we use it here */ +extern struct gpmc *gpmc_cfg; + +/** + * @brief board_init - gpmc and basic setup as phase1 of boot sequence + * + * @return 0 + */ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* TODO: Dynamically pop out CS mapping and program accordingly */ + /* Configure devices for default ON ON ON settings */ + enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0], + CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M); + enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000, + GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000, + GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE, + GPMC_SIZE_16M); + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c) +#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b) + +/** + * @brief ether_init Take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + */ +static void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + writew(0x0, LAN_RESET_REGISTER); + do { + writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto reset_err_out; + --cnt; + } while (readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto reset_err_out; + --cnt; + } while (readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG); + udelay(1000); +reset_err_out: + return; + +#endif +} + +/** + * @brief misc_init_r - Configure SDP board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ + /* Partial setup: + * VAUX3 - 2.8V for DVI + * VPLL1 - 1.8V + * VDAC - 1.8V + * and turns on LEDA/LEDB (not needed ... NOP?) + */ + twl4030_power_init(); + + /* FIXME finish setup: + * VAUX1 - 2.8V for mainboard I/O + * VAUX2 - 2.8V for camera + * VAUX4 - 1.8V for OMAP3 CSI + * VMMC1 - 3.15V (init, variable) for MMC1 + * VMMC2 - 1.85V for MMC2 + * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM + * VPLL2 - 1.8V + */ + ether_init(); + + return 0; +} + +/** + * @brief set_muxconf_regs Setting up the configuration Mux registers + * specific to the hardware. Many pins need to be moved from protect + * to primary mode. + */ +void set_muxconf_regs(void) +{ + /* platform specific muxes */ + MUX_SDP3430(); +} |