omap5: Add minimal support for omap5430.

This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.

OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

3 files changed, 79 insertions, 4 deletions

diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
index ec493f5..b299e2f 100644
--- a/board/ti/panda/Makefile
+++ b/board/ti/panda/Makefile
@@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-ifndef CONFIG_SPL_BUILD
 COBJS	:= panda.o
-endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 97320cb..b4271fb 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -65,6 +65,23 @@ int misc_init_r(void)
 	return 0;
 }
 
+void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	if (omap_revision() >= OMAP4460_ES1_0)
+		do_set_mux(CONTROL_PADCONF_WKUP,
+				 wkup_padconf_array_essential_4460,
+				 sizeof(wkup_padconf_array_essential_4460) /
+				 sizeof(struct pad_conf_entry));
+}
+
 void set_muxconf_regs_non_essential(void)
 {
 	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
@@ -93,10 +110,18 @@ void set_muxconf_regs_non_essential(void)
 				sizeof(struct pad_conf_entry));
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0);
 	return 0;
 }
 #endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+	return 0x20;
+}
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index 83d0c3f..c05170e 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -28,6 +28,58 @@
 
 #include <asm/arch/mux_omap4.h>
 
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)},	 /* gpio_wk7, TPS */
+
+};
+
 const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
@@ -219,7 +271,7 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
 	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, M7},					/* safe mode */
+	{PAD1_FREF_CLK3_REQ, M7},		/* safe mode */
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD0_FREF_CLK4_OUT, (PTU | M3)},	/* led status_2 */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */