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authorSanjeev Premi <premi@ti.com>2011-07-18 09:20:15 -0400
committerU-Boot <uboot@aari01-12.(none)>2011-08-03 12:49:18 +0200
commit6921b314a855b3c4856ef5ef83315fe945de98b2 (patch)
tree6c075fd3aeb62dc952beea57b872ac4b12ff777f /board/ti/evm
parent80bb756dbeeedc9d8a1cd7456b8d98c08ed303f1 (diff)
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omap3evm: eth: split function setup_net_chip
In current implementation, the function sets up the ethernet chip and resets it. The steps to reset depend upon the board revision. The patch moves the reset actions to new function reset_net_chip(). Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'board/ti/evm')
-rw-r--r--board/ti/evm/evm.c12
-rw-r--r--board/ti/evm/evm.h1
2 files changed, 12 insertions, 1 deletions
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index aaf3033..8f9f141 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -130,6 +130,9 @@ int misc_init_r(void)
#endif
omap3_evm_get_revision();
+#if defined(CONFIG_CMD_NET)
+ reset_net_chip();
+#endif
dieid_num_r();
return 0;
@@ -153,7 +156,6 @@ void set_muxconf_regs(void)
*/
static void setup_net_chip(void)
{
- struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */
@@ -172,6 +174,14 @@ static void setup_net_chip(void)
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
&ctrl_base->gpmc_nadv_ale);
+}
+
+/**
+ * Reset the ethernet chip.
+ */
+static void reset_net_chip(void)
+{
+ struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
/* Make GPIO 64 as output pin */
writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h
index b721ad6..623cf1b 100644
--- a/board/ti/evm/evm.h
+++ b/board/ti/evm/evm.h
@@ -49,6 +49,7 @@ u32 get_omap3_evm_rev(void);
#if defined(CONFIG_CMD_NET)
static void setup_net_chip(void);
+static void reset_net_chip(void);
#endif
/*