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authorMugunthan V N <mugunthanvnm@ti.com>2015-06-22 14:43:10 +0530
committerTom Rini <trini@konsulko.com>2015-07-07 20:15:52 -0400
commit0a888f584c48984cb9657a5d42dc994b33c264a7 (patch)
tree9b9755bc214a188d8f303f591e5a4da7fe5a16ff /board/ti/dra7xx
parent3cbb15d04f77d39e176253c537798f9e66b57082 (diff)
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ARM: DRA72x: fix io delay calibration for ethernet
we currently use in-development IODelay values for DRA72x which are proposed in the data sheet, however, DRA72x EVM uses DP83865 ethernet Phy over RGMII. The PHY characteristics and routing choices made on the EVM, make the current iodelay values fail ethernet communication. Instead, we need to choose custom values for DRA72x-evm specifically designed for the PHY and routing on the platform for ethernet to function. Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Diffstat (limited to 'board/ti/dra7xx')
-rw-r--r--board/ti/dra7xx/mux_data.h49
1 files changed, 25 insertions, 24 deletions
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index c9301a5..5145301 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -156,30 +156,31 @@ const struct pad_conf_entry early_padconf[] = {
#ifdef CONFIG_IODELAY_RECALIBRATION
const struct iodelay_cfg_entry iodelay_cfg_array[] = {
- {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */
- {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */
- {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */
- {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */
- {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */
- {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */
- {0x740, 531, 120}, /* RGMMI0_TXC_OUT */
- {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */
- {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */
- {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */
- {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */
- {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */
- {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */
- {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */
- {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
- {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
- {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
- {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
- {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
- {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
- {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */
- {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */
- {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
- {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
+ {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
+ {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
+ {0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
+ {0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
+ {0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
+ {0x740, 0, 220}, /* RGMMI0_TXC_OUT */
+ {0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
+ {0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
+ {0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
+ {0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
+ {0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
+ /* These values are for using RGMII1 configuration on VIN2a_x pins. */
+ {0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
+ {0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
+ {0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
+ {0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
+ {0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
+ {0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
+ {0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
+ {0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
+ {0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
+ {0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
+ {0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
+ {0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
};
#endif