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authorPeter Barada <peter.barada@logicpd.com>2012-11-13 07:40:28 +0000
committerTom Rini <trini@ti.com>2012-12-10 08:54:02 -0700
commit8c4445d26633f43fcd04add3d6cdc3bc41d14841 (patch)
treee2cab89ccff5955681182e71200a8d1053585528 /board/ti/beagle
parentd7aff44a00e5de3de2ed18a3329edf5ff9d3aada (diff)
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Pass sdrc timing values through board_sdrc_timings structure
Instead of passing individual registers by value to board_get_mem_timings, pass a board_mem_timings structure pointer for the board files to fill in. Pass same structure pointer to write_sdrc_timings. This saves about 90 bytes of space in SPL. Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Diffstat (limited to 'board/ti/beagle')
-rw-r--r--board/ti/beagle/beagle.c53
1 files changed, 26 insertions, 27 deletions
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 6175e1d..4adf982 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -139,8 +139,7 @@ static int get_board_revision(void)
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int pop_mfr, pop_id;
@@ -151,29 +150,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
*/
identify_nand_chip(&pop_mfr, &pop_id);
- *mr = MICRON_V_MR_165;
+ timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_C4:
if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
/* 512MB DDR */
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
- *ctrla = NUMONYX_V_ACTIMA_165;
- *ctrlb = NUMONYX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
/* Beagleboard Rev C5, 256MB DDR */
- *mcfg = MICRON_V_MCFG_200(256 << 20);
- *ctrla = MICRON_V_ACTIMA_200;
- *ctrlb = MICRON_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
}
case REVISION_XM_A:
@@ -181,24 +180,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
case REVISION_XM_C:
if (pop_mfr == 0) {
/* 256MB DDR */
- *mcfg = MICRON_V_MCFG_200(256 << 20);
- *ctrla = MICRON_V_ACTIMA_200;
- *ctrlb = MICRON_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
} else {
/* 512MB DDR */
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
- *ctrla = NUMONYX_V_ACTIMA_165;
- *ctrlb = NUMONYX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
break;
default:
/* Assume 128MB and Micron/165MHz timings to be safe */
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}
#endif