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| author | Anna, Suman <s-anna@ti.com> | 2016-05-23 13:32:16 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-06-02 21:42:17 -0400 |
| commit | e42523f54434119609744a62dcc9173b3a50dc29 (patch) | |
| tree | 815372d3028fdf83a3cb13d98abb37bfe81a3d71 /board/ti/am57xx/board.c | |
| parent | 27c9596f680ecea01beb52181da72b7d7fab0d8c (diff) | |
| download | u-boot-imx-e42523f54434119609744a62dcc9173b3a50dc29.zip u-boot-imx-e42523f54434119609744a62dcc9173b3a50dc29.tar.gz u-boot-imx-e42523f54434119609744a62dcc9173b3a50dc29.tar.bz2 | |
ARM: DRA7: Consolidate voltage macros across different SoCs
The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.
This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/ti/am57xx/board.c')
| -rw-r--r-- | board/ti/am57xx/board.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 28db532..da5f499 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -216,34 +216,34 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) } struct vcores_data beagle_x15_volts = { - .mpu.value = VDD_MPU_DRA752, + .mpu.value = VDD_MPU_DRA7, .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - .eve.value = VDD_EVE_DRA752, + .eve.value = VDD_EVE_DRA7, .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - .gpu.value = VDD_GPU_DRA752, + .gpu.value = VDD_GPU_DRA7, .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS45, .gpu.pmic = &tps659038, .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - .core.value = VDD_CORE_DRA752, + .core.value = VDD_CORE_DRA7, .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS6, .core.pmic = &tps659038, - .iva.value = VDD_IVA_DRA752, + .iva.value = VDD_IVA_DRA7, .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS45, |