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| author | Tom Rini <trini@ti.com> | 2015-06-05 15:51:11 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-06-15 10:57:26 -0400 |
| commit | 7c352cd38d0ad7a25f98592182704667dfde37a8 (patch) | |
| tree | ab155ec66d04a7a7e7096cb41fdf1eeaa1d200bb /board/ti/am43xx/board.c | |
| parent | 37be54fd1351a177c061c2c351ffdd53efaebb59 (diff) | |
| download | u-boot-imx-7c352cd38d0ad7a25f98592182704667dfde37a8.zip u-boot-imx-7c352cd38d0ad7a25f98592182704667dfde37a8.tar.gz u-boot-imx-7c352cd38d0ad7a25f98592182704667dfde37a8.tar.bz2 | |
am33xx: Re-enable SW levelling for DDR2
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet. In other cases
update the call to be as functional as before and check an already
programmed value in.
Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/ti/am43xx/board.c')
| -rw-r--r-- | board/ti/am43xx/board.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 4aae230..d7b9e5a 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -148,6 +148,29 @@ static const struct dpll_params idk_dpll_ddr = { 400, 23, 1, -1, 2, -1, -1 }; +static const u32 ext_phy_ctrl_const_base_lpddr2[] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + const struct ctrl_ioregs ioregs_lpddr2 = { .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, @@ -318,6 +341,16 @@ static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { .emif_cos_config = 0x00ffffff }; +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + if (board_is_eposevm()) { + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } + + return; +} + /* * get_sys_clk_index : returns the index of the sys_clk read from * ctrl status register. This value is either |