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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-01 15:11:18 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-01 15:11:18 +0200 |
commit | e99f30e105a253ee64bef1ef83b86a47e0d3b6f1 (patch) | |
tree | 847e087ca50c1d0a02b750577b13af45aa498361 /board/ti/am43xx/board.c | |
parent | d6694aff569a0838a9d0ef352128f5aa309d73ff (diff) | |
parent | 12cc54376768461533b55ada1b0b6d4979f40579 (diff) | |
download | u-boot-imx-e99f30e105a253ee64bef1ef83b86a47e0d3b6f1.zip u-boot-imx-e99f30e105a253ee64bef1ef83b86a47e0d3b6f1.tar.gz u-boot-imx-e99f30e105a253ee64bef1ef83b86a47e0d3b6f1.tar.bz2 |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'board/ti/am43xx/board.c')
-rw-r--r-- | board/ti/am43xx/board.c | 79 |
1 files changed, 77 insertions, 2 deletions
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 71af1ae..054a452 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -217,6 +217,28 @@ const struct emif_regs ddr3_emif_regs_400Mhz = { .emif_rd_wr_exec_thresh = 0x00000405 }; +static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { + .sdram_config = 0x638413b2, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00000c30, + .sdram_tim1 = 0xeaaad4db, + .sdram_tim2 = 0x266b7fda, + .sdram_tim3 = 0x107f8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074be4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0e084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x89, + .emif_ddr_ext_phy_ctrl_3 = 0x90, + .emif_ddr_ext_phy_ctrl_4 = 0x8e, + .emif_ddr_ext_phy_ctrl_5 = 0x8d, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000000, +}; + const u32 ext_phy_ctrl_const_base_ddr3[] = { 0x00400040, 0x00350035, @@ -240,6 +262,48 @@ const u32 ext_phy_ctrl_const_base_ddr3[] = { 0x08102040 }; +static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = { + /* first 5 are taken care by emif_regs */ + 0x00700070, + + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + + 0x00150015, + 0x00150015, + 0x00150015, + 0x00150015, + 0x00150015, + + 0x00800080, + 0x00800080, + + 0x40000000, + + 0x08102040, + + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { @@ -248,6 +312,9 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) } else if (board_is_gpevm()) { *regs = ext_phy_ctrl_const_base_ddr3; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); + } else if (board_is_sk()) { + *regs = ext_phy_ctrl_const_base_ddr3_sk; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); } return; @@ -257,10 +324,10 @@ const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) return &epos_evm_dpll_ddr; - else if (board_is_gpevm()) + else if (board_is_gpevm() || board_is_sk()) return &gp_evm_dpll_ddr; - puts(" Board not supported\n"); + printf(" Board '%s' not supported\n", am43xx_board_name); return NULL; } @@ -410,6 +477,9 @@ void sdram_init(void) enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz, 0); + } else if (board_is_sk()) { + config_ddr(400, &ioregs_ddr3, NULL, NULL, + &ddr3_sk_emif_regs_400Mhz, 0); } } #endif @@ -524,6 +594,11 @@ int board_eth_init(bd_t *bis) writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; cpsw_slaves[0].phy_addr = 16; + } else if (board_is_sk()) { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; + cpsw_slaves[0].phy_addr = 4; + cpsw_slaves[1].phy_addr = 5; } else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; |