diff options
| author | Tom Rini <trini@ti.com> | 2013-06-22 07:38:12 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-06-22 07:38:12 -0400 |
| commit | 348e47f766ac228fb02d1af562b2e9a4c69355db (patch) | |
| tree | 778ffb90bb670f45fa7a0dae78010c8128c4d84d /board/ti/am335x | |
| parent | 5707233880090f785c33df32c04549ea1aeef61e (diff) | |
| parent | fbf87b1823dd5ebc2a384711ea2c677543019ece (diff) | |
| download | u-boot-imx-348e47f766ac228fb02d1af562b2e9a4c69355db.zip u-boot-imx-348e47f766ac228fb02d1af562b2e9a4c69355db.tar.gz u-boot-imx-348e47f766ac228fb02d1af562b2e9a4c69355db.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'board/ti/am335x')
| -rw-r--r-- | board/ti/am335x/board.c | 39 |
1 files changed, 1 insertions, 38 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 638cc4d..fdbe26c 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -38,9 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#ifdef CONFIG_SPL_BUILD -static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; -#endif /* MII mode defines */ #define MII_MODE_ENABLE 0x0 @@ -126,28 +123,7 @@ static int read_eeprom(void) return 0; } -/* UART Defines */ #ifdef CONFIG_SPL_BUILD -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -static void rtc32k_enable(void) -{ - struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; - - /* - * Unlock the RTC's registers. For more details please see the - * RTC_SS section of the TRM. In order to unlock we need to - * write these specific values (keys) in this order. - */ - writel(0x83e70b13, &rtc->kick0r); - writel(0x95a4f1e0, &rtc->kick1r); - - /* Enable the RTC 32K OSC by setting bits 3 and 6. */ - writel((1 << 3) | (1 << 6), &rtc->osc); -} - static const struct ddr_data ddr2_data = { .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | (MT47H128M16RT25E_RD_DQS<<20) | @@ -339,9 +315,6 @@ void s_init(void) /* Enable RTC32K clock */ rtc32k_enable(); - /* UART softreset */ - u32 regVal; - #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); #endif /* CONFIG_SERIAL1 */ @@ -361,17 +334,7 @@ void s_init(void) enable_uart5_pin_mux(); #endif /* CONFIG_SERIAL6 */ - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_RESET; - writel(regVal, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & - UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_SMART_IDLE_EN; - writel(regVal, &uart_base->uartsyscfg); + uart_soft_reset(); gd = &gdata; |