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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-01-08 13:15:45 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-01-08 13:15:45 +0100
commit79f38777947ac7685e2cef8bd977f954ab198c0e (patch)
tree6fe053ef751b1c424ec50be338844197b6421d74 /board/ti/am335x
parent96764df1b47ddebfb50fadf5af72530b07b5fc89 (diff)
parent9bd5c1ad0db802c9f8d49d72b443f03431cf6a89 (diff)
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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This required manual merging drivers/mtd/nand/Makefile and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
Diffstat (limited to 'board/ti/am335x')
-rw-r--r--board/ti/am335x/board.c4
-rw-r--r--board/ti/am335x/mux.c22
2 files changed, 25 insertions, 1 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index f0eca54..ed4229e 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -44,7 +44,7 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0xA
+#define RGMII_MODE_ENABLE 0x3A
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
@@ -318,6 +318,8 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gpmc_init();
+
return 0;
}
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 8437ef5..0283708 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -171,6 +171,25 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1},
};
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
@@ -257,6 +276,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
/* In profile #2 i2c1 and spi0 conflict. */
if (profile & ~PROFILE_2)
configure_module_pin_mux(i2c1_pin_mux);
+ /* Profiles 2 & 3 don't have NAND */
+ if (profile & ~(PROFILE_2 | PROFILE_3))
+ configure_module_pin_mux(nand_pin_mux);
else if (profile == PROFILE_2) {
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);