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| author | Ilya Yanok <ilya.yanok@cogentembedded.com> | 2012-11-06 13:06:29 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-12-10 08:54:01 -0700 |
| commit | 70fb65b093dd10a26c3e5e09f0e9cef3cc215ffd (patch) | |
| tree | e890fdc0cc5d42fd84ff253378fca32d4268f466 /board/ti/am335x/mux.c | |
| parent | 1befaffbfb32d6db7f43613952f9fe82a6ced000 (diff) | |
| download | u-boot-imx-70fb65b093dd10a26c3e5e09f0e9cef3cc215ffd.zip u-boot-imx-70fb65b093dd10a26c3e5e09f0e9cef3cc215ffd.tar.gz u-boot-imx-70fb65b093dd10a26c3e5e09f0e9cef3cc215ffd.tar.bz2 | |
am335x_evm: add nand pinmux definition
Add NAND pins mux settings for AM335X devices. Enable NAND pins
for AM335X EVM board.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Diffstat (limited to 'board/ti/am335x/mux.c')
| -rw-r--r-- | board/ti/am335x/mux.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 8437ef5..0283708 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -171,6 +171,25 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -257,6 +276,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) /* In profile #2 i2c1 and spi0 conflict. */ if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); + /* Profiles 2 & 3 don't have NAND */ + if (profile & ~(PROFILE_2 | PROFILE_3)) + configure_module_pin_mux(nand_pin_mux); else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); |