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authorTom Rini <trini@ti.com>2014-07-07 21:40:16 -0400
committerTom Rini <trini@ti.com>2014-07-25 16:26:08 -0400
commitc4f80f500356a8e0a71debe5bbe6e9a0d6d5d62e (patch)
tree29f973053d1afac41e1f69c43d083f473bc40853 /board/ti/am335x/board.c
parentc6ac7e3bdc195a7dd39b5bf699deceedb9444c0c (diff)
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am335x_evm / gumstix pepper: Correct DDR settings
As noted by clang, we have been shifting certain values out of 32bit range when setting some DDR registers. Upon further inspection these had been touching reserved fields (and having no impact). These came in from historical bring-up code and can be discarded. Similarly, we had been declaring some fields as 0 when they will be initialized that way. Tested on Beaglebone White. Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Ash Charles <ash@gumstix.com> Signed-off-by: Tom Rini <trini@ti.com> Tested-By: Ash Charles <ashcharles@gmail.com>
Diffstat (limited to 'board/ti/am335x/board.c')
-rw-r--r--board/ti/am335x/board.c30
1 files changed, 3 insertions, 27 deletions
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index da780ed..d81eec9 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
- (MT47H128M16RT25E_RD_DQS<<20) |
- (MT47H128M16RT25E_RD_DQS<<10) |
- (MT47H128M16RT25E_RD_DQS<<0)),
- .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
- (MT47H128M16RT25E_WR_DQS<<20) |
- (MT47H128M16RT25E_WR_DQS<<10) |
- (MT47H128M16RT25E_WR_DQS<<0)),
- .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
- (MT47H128M16RT25E_PHY_WRLVL<<20) |
- (MT47H128M16RT25E_PHY_WRLVL<<10) |
- (MT47H128M16RT25E_PHY_WRLVL<<0)),
- .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
- (MT47H128M16RT25E_PHY_GATELVL<<20) |
- (MT47H128M16RT25E_PHY_GATELVL<<10) |
- (MT47H128M16RT25E_PHY_GATELVL<<0)),
- .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
- (MT47H128M16RT25E_PHY_WR_DATA<<20) |
- (MT47H128M16RT25E_PHY_WR_DATA<<10) |
- (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {