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author | Stefano Babic <sbabic@denx.de> | 2012-08-29 01:22:07 +0000 |
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committer | Tom Rini <trini@ti.com> | 2012-09-04 17:05:39 -0700 |
commit | 629868755703aa173458531537cb8c4b570ed47c (patch) | |
tree | 6ee545d7a751dd8d89d7e4e8fd28e1fce348b789 /board/teejet | |
parent | fb380bfa8c0b841dff973bb6c74b2b5e40fe64f4 (diff) | |
download | u-boot-imx-629868755703aa173458531537cb8c4b570ed47c.zip u-boot-imx-629868755703aa173458531537cb8c4b570ed47c.tar.gz u-boot-imx-629868755703aa173458531537cb8c4b570ed47c.tar.bz2 |
OMAP3: mt_ventoux: added video support
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/teejet')
-rw-r--r-- | board/teejet/mt_ventoux/mt_ventoux.c | 83 | ||||
-rw-r--r-- | board/teejet/mt_ventoux/mt_ventoux.h | 2 |
2 files changed, 84 insertions, 1 deletions
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 814e72f..b8ad447 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -21,13 +21,17 @@ #include <common.h> #include <netdev.h> +#include <malloc.h> #include <fpga.h> +#include <video_fb.h> #include <asm/io.h> #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/omap_gpio.h> #include <asm/arch/mmc_host_def.h> +#include <asm/arch/dss.h> +#include <asm/arch/clocks.h> #include <i2c.h> #include <spartan3.h> #include <asm/gpio.h> @@ -53,6 +57,42 @@ DECLARE_GLOBAL_DATA_PTR; #define FPGA_INIT 119 #define FPGA_DONE 154 +#define LCD_PWR 138 +#define LCD_PON_PIN 139 + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct { + u32 xres; + u32 yres; +} panel_resolution[] = { + { 480, 272 }, + { 800, 480 } +}; + +static struct panel_config lcd_cfg[] = { + { + .timing_h = PANEL_TIMING_H(4, 8, 41), + .timing_v = PANEL_TIMING_V(2, 4, 10), + .pol_freq = 0x00000000, /* Pol Freq */ + .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = 0, + }, + { + .timing_h = PANEL_TIMING_H(20, 192, 4), + .timing_v = PANEL_TIMING_V(2, 20, 10), + .pol_freq = 0x00004000, /* Pol Freq */ + .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = 0, + } +}; +#endif + /* Timing definitions for FPGA */ static const u32 gpmc_fpga[] = { FPGA_GPMC_CONFIG1, @@ -254,3 +294,46 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0); } #endif + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +int board_video_init(void) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + struct panel_config *panel = &lcd_cfg[0]; + char *s; + u32 index = 0; + + void *fb; + + fb = (void *)0x88000000; + + s = getenv("panel"); + if (s) { + index = simple_strtoul(s, NULL, 10); + if (index < ARRAY_SIZE(lcd_cfg)) + panel = &lcd_cfg[index]; + else + return 0; + } + + panel->frame_buffer = fb; + printf("Panel: %dx%d\n", panel_resolution[index].xres, + panel_resolution[index].yres); + panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | + (panel_resolution[index].xres - 1); + + gpio_request(LCD_PWR, "LCD Power"); + gpio_request(LCD_PON_PIN, "LCD Pon"); + gpio_direction_output(LCD_PWR, 0); + gpio_direction_output(LCD_PON_PIN, 1); + + + setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); + setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); + + omap3_dss_panel_config(panel); + omap3_dss_enable(); + + return 0; +} +#endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h index eadb8a5..1cd7ec2 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.h +++ b/board/teejet/mt_ventoux/mt_ventoux.h @@ -203,7 +203,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ /* GPIO_138: LCD_ENVD */\ - MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \ /* GPIO_139: LCD_PON */\ /* McBSP */\ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ |