MA-7455-1 Pico: modify Pico configuration for Brillo.

Modify the picosom to be suit for Brillo configurations.

Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com>
(cherry picked from commit 864fd4f019674e8333b1fdb91e9242ae75f35992)
To align with 2016.03, fix several places.
Signed-off-by: Peng Fan <peng.fan@nxp.com>

2 files changed, 24 insertions, 68 deletions

diff --git a/board/technexion/picosom-imx6ul/Kconfig b/board/technexion/picosom-imx6ul/Kconfig
index ac5e24a..72980e9 100644
--- a/board/technexion/picosom-imx6ul/Kconfig
+++ b/board/technexion/picosom-imx6ul/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
 config SYS_VENDOR
 	default "technexion"
 
-config SYS_SOC
-	default "mx6"
-
 config SYS_CONFIG_NAME
 	default "picosom-imx6ul"
 
diff --git a/board/technexion/picosom-imx6ul/picosom-imx6ul.c b/board/technexion/picosom-imx6ul/picosom-imx6ul.c
index 7b07d6d..71a3cc6 100644
--- a/board/technexion/picosom-imx6ul/picosom-imx6ul.c
+++ b/board/technexion/picosom-imx6ul/picosom-imx6ul.c
@@ -31,7 +31,7 @@
 
 #ifdef CONFIG_POWER
 #include <power/pmic.h>
-#include <power/pfuze300_pmic.h>
+#include <power/pfuze3000_pmic.h>
 #include "../../freescale/common/pfuze.h"
 #endif
 
@@ -379,16 +379,9 @@ static iomux_v3_cfg_t const lcd_pads[] = {
 	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-struct lcd_panel_info_t {
-	unsigned int lcdif_base_addr;
-	int depth;
-	void (*enable)(struct lcd_panel_info_t const *dev);
-	struct fb_videomode mode;
-};
-
-void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
+void do_enable_parallel_lcd(struct display_info_t const *dev)
 {
-	enable_lcdif_clock(dev->lcdif_base_addr);
+	enable_lcdif_clock(dev->bus);
 
 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
@@ -401,9 +394,10 @@ void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
 	gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
 }
 
-static struct lcd_panel_info_t const displays[] = {{
-	.lcdif_base_addr = LCDIF1_BASE_ADDR,
-	.depth = 24,
+static struct display_info_t const displays[] = {{
+	.lcdif_base_addr = MX6UL_LCDIF1_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
 	.enable	= do_enable_parallel_lcd,
 	.mode	= {
 		.name			= "TFT43AB",
@@ -419,42 +413,7 @@ static struct lcd_panel_info_t const displays[] = {{
 		.sync           = 0,
 		.vmode          = FB_VMODE_NONINTERLACED
 } } };
-
-int board_video_skip(void)
-{
-	int i;
-	int ret;
-	char const *panel = getenv("panel");
-	if (!panel) {
-		panel = displays[0].mode.name;
-		printf("No panel detected: default to %s\n", panel);
-		i = 0;
-	} else {
-		for (i = 0; i < ARRAY_SIZE(displays); i++) {
-			if (!strcmp(panel, displays[i].mode.name))
-				break;
-		}
-	}
-	if (i < ARRAY_SIZE(displays)) {
-		ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
-				    displays[i].lcdif_base_addr);
-		if (!ret) {
-			if (displays[i].enable)
-				displays[i].enable(displays+i);
-			printf("Display: %s (%ux%u)\n",
-			       displays[i].mode.name,
-			       displays[i].mode.xres,
-			       displays[i].mode.yres);
-		} else
-			printf("LCD %s cannot be configured: %d\n",
-			       displays[i].mode.name, ret);
-	} else {
-		printf("unsupported panel %s\n", panel);
-		return -EINVAL;
-	}
-
-	return 0;
-}
+size_t display_count = ARRAY_SIZE(displays);
 #endif
 
 #ifdef CONFIG_FEC_MXC
@@ -568,35 +527,35 @@ int power_init_board(void)
 	int ret;
 	unsigned int reg, rev_id;
 
-	ret = power_pfuze300_init(I2C_PMIC);
+	ret = power_pfuze3000_init(I2C_PMIC);
 	if (ret)
 		return ret;
 
-	pfuze = pmic_get("PFUZE300");
+	pfuze = pmic_get("PFUZE3000");
 	ret = pmic_probe(pfuze);
 	if (ret)
 		return ret;
 
-	pmic_reg_read(pfuze, PFUZE300_DEVICEID, &reg);
-	pmic_reg_read(pfuze, PFUZE300_REVID, &rev_id);
-	printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+	pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
+	pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 
 	/* disable Low Power Mode during standby mode */
-	pmic_reg_read(pfuze, PFUZE300_LDOGCTL, &reg);
+	pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
 	reg |= 0x1;
-	pmic_reg_write(pfuze, PFUZE300_LDOGCTL, reg);
+	pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
 
 	/* SW1B step ramp up time from 2us to 4us/25mV */
 	reg = 0x40;
-	pmic_reg_write(pfuze, PFUZE300_SW1BCONF, reg);
+	pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
 
 	/* SW1B mode to APS/PFM */
 	reg = 0xc;
-	pmic_reg_write(pfuze, PFUZE300_SW1BMODE, reg);
+	pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
 
 	/* SW1B standby voltage set to 0.975V */
 	reg = 0xb;
-	pmic_reg_write(pfuze, PFUZE300_SW1BSTBY, reg);
+	pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
 
 	return 0;
 }
@@ -618,18 +577,18 @@ void ldo_mode_set(int ldo_bypass)
 	if (ldo_bypass) {
 		prep_anatop_bypass();
 		/* decrease VDDARM to 1.275V */
-		pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
+		pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value);
 		value &= ~0x1f;
-		value |= PFUZE300_SW1AB_SETP(1275);
-		pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
+		value |= PFUZE3000_SW1AB_SETP(1275);
+		pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value);
 
 		set_anatop_bypass(1);
-		vddarm = PFUZE300_SW1AB_SETP(1175);
+		vddarm = PFUZE3000_SW1AB_SETP(1175);
 
-		pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
+		pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value);
 		value &= ~0x1f;
 		value |= vddarm;
-		pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
+		pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value);
 
 		finish_anatop_bypass();