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authorwdenk <wdenk>2005-04-02 23:52:25 +0000
committerwdenk <wdenk>2005-04-02 23:52:25 +0000
commit400558b561e2bdb47f87b96b3510dda0881a3662 (patch)
tree479fa3918e0031a95cdac9468cb8396e1f1a9b60 /board/tb0229/lowlevel_init.S
parent414eec35e3832f4f9ce8a25ace7ead638be1f76f (diff)
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Prepare for SoC rework of ARM code:
- rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL - rename memsetup into lowlevel_init (function name and source files)
Diffstat (limited to 'board/tb0229/lowlevel_init.S')
-rw-r--r--board/tb0229/lowlevel_init.S71
1 files changed, 71 insertions, 0 deletions
diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S
new file mode 100644
index 0000000..df31806
--- /dev/null
+++ b/board/tb0229/lowlevel_init.S
@@ -0,0 +1,71 @@
+/*
+ * Memory sub-system initialization code for TANBAC Evaluation board TB0229.
+ *
+ * Copyright (c) 2003 Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+
+ .globl lowlevel_init
+lowlevel_init:
+
+ /* BCUCNTREG1 = 0x0040 */
+ la t0, 0xaf000000
+ li t1, 0x0040
+ sh t1, 0(t0)
+
+ /* ROMSIZEREG = 0x3333 */
+ la t0, 0xaf000004
+ li t1, 0x3333
+ sh t1, 0(t0)
+
+ /* ROMSPEEDREG = 0x3003 */
+ la t0, 0xaf000006
+ li t1, 0x3003
+ sh t1, 0(t0)
+
+ /* BCUCNTREG3 = 0 */
+ la t0, 0xaf000016
+ li t1, 0x0000
+ sh t1, 0(t0)
+
+ /* CMUCLKMSK */
+ la t0, 0xaf000060
+ li t1, 0x39a2
+ sh t1, 0(t0)
+
+ /* PMUCNTREG */
+ la t0, 0xaf0000c2
+ li t1, 0x0006
+ sh t1, 0(t0)
+
+ /* SDRAMMODEREG = 0x8029 */
+ la t0, 0xaf000400
+ li t1, 0x8029
+ sh t1, 0(t0)
+
+ /* SDRAMCNTREG = 0x2322 */
+ la t0, 0xaf000402
+ li t1, 0x2322
+ sh t1, 0(t0)
+
+ /* BCURFCNTREG = 0x0106 */
+ la t0, 0xaf000404
+ li t1, 0x0106
+ sh t1, 0(t0)
+
+ /* RAMSZEREG = 0x5555 (64MB Bank) */
+ la t0, 0xaf000408
+ li t1, 0x5555
+ sh t1, 0(t0)
+
+ j ra
+ nop